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We report recent advances in tool and process hardening of a first of its kind 300 mm wafer-to-wafer (WtW) preprocessing, aligning, and bonding integrated tool. We have demonstrated sub-500 nm post-bond alignment accuracies for 300 mm WtW face-to-face (FtF) Cu-Cu thermocompression bonds, WtW FtF Si-Si fusion bonds, and WtW FtF oxideoxide fusion bonds. All process of record (POR) recipes that were...
Focused Ion Beam (FIB) milling has been widely used for the preparation of TEM specimens in both cross-section and plan view configurations. FIB induced damage is a non-negligible influence on making a thin and clear TEM specimen. Low-KV FIB is one of the solutions to reduce the ion beam damage created in current FIB operation system. An understanding of the type of FIB generated artifact on different...
A transparent layer consisting of ordered arrays of core/shell cadmium selenide(CdSe)/zinc sulfide(ZnS) quantum dots(QDs) sandwiched in thin silicon dioxide (SiO2) layers has been prepared by embedment of films of QDs in oxide layer deposited by electron beam (e-beam) to use as spectral down shifter. Well ordered nanostructures are revealed by TEM and excitonic photoluminescence (PL) spectra. Low...
We report on recent experimental studies performed as part of a 3D integrated circuit (3DIC) production-worthy process module roadmap check for 300 mm wafer-to-wafer (WtW) copper-to-copper thermocompression bonding and face-to-face (F2F) aligning. Specifically, we demonstrate submicron alignment capabilities (3sigma alignment variability ~ 1 μm) post Cu bonding on topography M1V1-to-M2 Cu wafers with...
The potential for via-mid through-silicon vias (TSVs) can be considerable, since their use allows not only a reduction in interconnect length from several mm to several microns, but also a tremendous increase in bandwidth between the stacked chips. The net result is less power consumption, higher performance, increased device density within a given chip footprint, and greater potential to integrate...
Nano-layered films of Cu/Cu(Zr)/Zr(Ge) and Cu/Cu(Zr) were deposited on the Si/SiOC:H substrates by magnetron sputtering. Samples were subsequently annealed at temperatures ranging from 350~500??C in vacuum, and characterized by four-point probe technique, glancing incident angle X-ray diffraction, Auger electron spectroscopy (AES) and transmission electron microscopy. The results indicated that the...
Vertically aligned copper indium diselenide nanorod arrays were synthesized by electrodeposition using porous anodic alumina template supported on a tungsten/silicon substrate. Porous anodic alumina template was fabricated by anodizing aluminium film which was sputtered onto tungsten/silicon substrate. The approach employed a selective chemical etching to penetrate the barrier layer at the bottom...
Cu metallization has been widely applied in back-end-of-line (BEOL) of integrated circuit fabrication, as well as in advanced packaging such as 3-D interconnects and through silicon via (TSV). As the device feature size further shrinks copper diffusion barrier layers with high conductivity, good thermal stability and low Cu diffusion coefficient are to be developed. Amorphous metal alloy films of...
Regularly faceted copper (Cu) particles ranging from tens of nanometers to submicron were obtained by annealing Cu-Zr films on polyimide and single Si (100) substrates. XRD, TEM, SEM and EDS were used to characterize their microstructural properties. The results show that these particles are pure Cu element and single crystals with [111] preferred orientation. Systematical analysis demonstrates that...
The nano-mechanical properties of as-deposited Cu/Si thin films indented to a depth of 2000 nm are investigated using a nanoindentation technique. The nanoindented specimens are annealed at a temperature of either 160°C or 210°C, respectively. The microstructures of the as-deposited and annealed samples are then examined via transmission electron microscopy (TEM). The results show that both the loading...
This paper presents a study on the contact resistance of interconnects between chip and package of embedded chip technology. Multi-layered aluminum/titanium tungsten/copper interconnects (Al/TiW/Cu) were used as the model system. Design of experiment was carried out to characterize the effect of under bump metallurgy deposition steps, including the degas and radio frequency (RF) plasma etch steps,...
The [110]-textured extremely thin Nb barrier layer is prepared on an amorphous SiO2 substrate, on which the preferentially oriented Cu [111] texture is obtained. Transmission Electron Microscopy (TEM) observation indicates that nanocrystalline grains no larger than ~10 nm with a spread [110] orientation along the substrate normal direction is characteristic of a 10 nm thick Nb barrier on SiO2, whereas...
An independent-gate four-terminal FinFET SRAM have been successfully fabricated for drastic leakage current reduction. The new SRAM is consisted of a four-terminal (4T-) FinFET which has a flexible Vth controllability. The 4T-FinFET with a TiN metal gate is fabricated by a newly developed gate separation etching process. By appropriately controlling the Vth of the 4T-FinFET, we have successfully demonstrated...
Bulk nanostructured (Bi,Sb)2Te3 compounds and GeTe based amorphous/nanocrystal composites have been successfully fabricated by the combined hydrothermal/hot-pressing and quenching/annealing methods, respectively. The (Bi,Sb)2Te3 nanopowders synthesized by hydrothermal method exhibit a hollow-like structure. After hot-pressing, the nanoscale grains varying from tens to hundreds of nanometers were found...
Nanostructuring is one of the effective approaches to lower the thermal conductivity of materials. Nanostructured skutterudite-related compounds CoSb3, Fe0.5Ni0.5Sb3, Fe0.25Ni0.25Co0.5Sb3 and Te-doped CoSb3 were synthesized by a solvothermal route. The bulk materials were prepared by hot pressing or spark plasma sintering from the solvothermally synthesized nanopowders. The thermal conductivity values...
We evaluated the electrical properties and change of nanostructure of Cu doped SiO2 and Ge2Sb2Te5 (GST) thin film under electrical stressing. Specialized scanning tunneling microscopy (STM)-transmission electron microscope (TEM) holder, which allows us to do the electrical characterization and observation of in-situ nano-structural evolution simultaneously, used as a approach method to confirm the...
In this paper, we present transmission electron microscopy (TEM) investigations of a potential failure mode for Cu lines subjected to alternating thermal loads. Wide Cu lines with 200 nm thickness were produced on a Si/SiO2/SiNx wafer by a series of conventional microfabrication steps. Alternating currents (AC) with a frequency of 100 Hz was then applied to the Cu lines and produced temperature cycles...
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