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Direct Cu-Cu bonding has been pursued by the semiconductor industry as the next interconnection node, for its superior power-handling capability, thermal stability and reliability as compared to traditional solders. However, manufacturability of Cu interconnections has so far been severely limited by the relatively high modulus of Cu, requiring costly planarization processes to address non-coplanarities...
The properties of ultrathin RuC film and RuC/TaN stack as the Cu diffusion barrier on Si substrate were studied. The results show that the thermal stability of the Cu/RuC/TaN/Si structure is better than that of the Cu/Ru/TaN/Si structure. A flush TaN layer can improve the thermal stability of RuC film and make it a more robust diffusion barrier for Cu metallization.
In recent years, through wafer electrical connections have become important roles, which will be used in developing high-speed, compact 3D microelectronic devices in next generation. Although the electroplating copper is a well-established process, completely void-free electroplating in through silicon holes (TSH) with a high aspect ratio remains a big challenge. Naturally, local current distribution...
The paper describes the problems of interconnecting single solar cells with each other to create a photovoltaic module. High power und low voltages demand the transport of high currents through the interconnection wires. The resistance of the wiring is crucial, because it significantly influences the total module efficiency. However, increasing the width and height of the rectangular wires leads to...
Three-dimensional (3D) chip stacks are receiving more attention for system performance enhancements. However, because of the higher circuit density, the cooling of 3D chip stacks gets more challenging. In conventional cooling methods, a heat sink or a micro-channel cooler is located at the top of the chip to dissipate the generated heat in a chip. In this paper, possible cooling methods from the bottom...
This article discusses the potential of surface activation based nanobonding technologies. Three-strategies of the nanobonding technologies with a number of applications such as the bonding of copper nanobumps, III-V materials and ionic materials have been discussed.
A novel test structure based on a planar capacitor design has been used for advanced barrier material evaluation and process optimization. This structure enables intrinsic reliability study of Cu/low-k interconnects. Various barrier materials such as CuMn self-forming barrier, ALD Ru, and PVD TaNTa on different dielectric films have been investigated to understand their intrinsic limits of barrier...
PoP structures have been used widely in digital consumer electronics products such as digital still cameras and mobile phones. However, the final stack height from the top to the bottom package for these structures is higher than that of the current stacked die packages. To reduce the height of the package, a flip chip technology is used. Since the logic chips of mobile applications use a pad pitch...
Three-dimensional (3-D) wafer stacking technologies offer new possibilities in terms of device architecture and miniaturization. To stack wafers, reliable through-silicon vias (TSVs) and interconnections must be processed into ultrathin wafers, and such processing is made possible by new methods for wafer handling. Of the different wafer-level bonding techniques, temporary wafer bonding adhesives...
In recent years, in order to achieve high density and high transmission speed between chips, various kinds of silicon modules have been developed. Our purpose is the development of silicon module in which several chips are mounted on the silicon substrate with Cu-Through Silicon Vias (Cu-TSVs) and fine multilayer Cu wirings such as global layer of devices. Since silicon substrate has a quite flat...
This paper presents a study on the contact resistance of interconnects between chip and package of embedded chip technology. Multi-layered aluminum/titanium tungsten/copper interconnects (Al/TiW/Cu) were used as the model system. Design of experiment was carried out to characterize the effect of under bump metallurgy deposition steps, including the degas and radio frequency (RF) plasma etch steps,...
Due to large mismatch in coefficients of thermal expansion between the copper via and the silicon of Through Silicon Via(TSV), significant thermal stresses will be induced at the interfaces of copper/dielectric layer (usually SiO2) and dielectric layer/silicon when TSV structure is subjected to subsequent temperature loadings, which would influence the reliability and the electrical performance of...
Large thermal mismatch stress can be introduced in 3D-Integration structures employing Through-Silicon-Via (TSV). The stress distribution in silicon and interconnect is affected by the via diameter and layout geometry. The TSV induced stress changes silicon mobility and ultimately alters device performance. The mobility and performance change differs in nand p- silicon and is a function of the distance...
SiOCH low-k dielectrics introduction in copper interconnects associated to the critical dimensions reduction in sub 45 nm technology nodes is a challenge for reliability engineers. Circuit wear-out linked to low-k dielectric breakdown is now becoming a major concern. With the reduction of the line to line spacing, the control of the copper line topology is becoming a first order parameter governing...
New developments in trench technology for power MOSFET's drives intrinsic electrical silicon resistance to a minimum. This implicates that the contribution of the package resistance becomes more significant in the total electrical resistance (Rdson) of the product. Low Rdson for power packages is an important characteristic. Within the package the electrical interconnect between die top and leadframe...
This paper reports the designing/simulation and experimental investigation into the Deep RIE-based micro-fabrication of through-Si-via (TSV) which acts as the vital vertical interconnect for compact 3-D system-in-package integration. An in-house developed process simulator based on cell/string evolution algorithm and physical modeling is used to explore suitable DRIE conditions for drilling vias with...
We have newly proposed heterogeneous multi-chip module integration technologies in which MEMS and LSI chips are mounted on Si or flexible substrates using a self-assembly method. A large numbers of chips were precisely and simultaneously self-assembled and bonded onto the substrates with high alignment accuracy of approximately 400 nm. Thick MEMS and LSI chips with a thickness of more than 100 mum...
The highest integration density of microsystems can be obtained using a 3D-stacking approach, where each layer of the stack is realized using a different technology, which may include sensors, imagers, rf and MEMS technologies. A key challenge is however to perform such stacking in a cost-effective manner. In this paper, a novel 3D TSV and 3D stacking technologies will be presented. Application examples...
In this paper, HfN on Si(100) has similar growth quality and electrical resistivity as HfN on MgO(100) (~30 muOmega-cm ), The resistivity values for HfN films on both substrates are much lower than that of TaN and TiN. Preliminary Cu diffusion test along with its low resistivity suggest that cubic HfN can be a promising candidate for Cu diffusion barriers.
The integration of electrochemically deposited copper into the wafer level packaging area has become an important and widely discussed topic. Besides the electrical and thermal advantages of copper interconnections, the dimensional stability is as well a beneficial feature for all new packaging designs and technologies. All corresponding industry applications, as there are copper pillar, redistribution...
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