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Emerging fan-out packages require advances in mold compounds, polymer interfaces to metals and silicon, and innovative processing to reach the required high reliability. In this paper, we discuss the fracture energy for mold compound interface to copper and silicon, and use that information for studying interfacial delamination propagation of mold compound. We have examined mold compound delamination...
The downscaling in VLSI systems and the use of new materials influences the reliability of components in terms of radiation more and more. The unavoidable presence of particle radiation on ground and in space leads to unwanted failures in the electronic devices. Concerning packaging materials, design and technology a lot of steps were done to avoid radiation sensitivity. Nowadays microelectronic for...
Wide band gap devices (e.g. Silicon Carbide, Gallium Nitride, etc.) provide significant opportunities for the power electronics industry. Compared to silicon, they have faster switching frequencies, better heat dissipation, and can operate at higher temperatures. But, WBG devices pose several challenges in terms of their packaging. This paper details the need for a co-design and simulation approach...
There is no doubt that component embedding technology becomes more visible in handheld applications like smart phones and wearables. Embedding technology is pushing the miniaturization which is a must for the next big wave of Wearable Electronics and Internet of Things (IoT). The technology is going to System in Package and the question today is how far you can go in miniaturization and how much of...
Silver sintering is a potential die attach technology to replace the solder technology for power electronic systems. A design of experiments (DoE) is performed in order to investigate the influences of sinter parameters as sinter pressure, temperature, duration, drying temperature and the interactions of these parameters on the shear strength of the Ag-sinter connection. Four sinter pastes have been...
We investigated why the blocking voltages of a power device are lowered during a durability test through a device simulation called Technology Computer Aided Design (TCAD) and measurements using the optical beam induced current (OBIC) method. We found that the spread of the depletion layer caused by the bonding wire is what decreased the blocking voltage.
As known to all, photometric and colorimetric quality of LED illumination mainly depends on LED chip, phosphor and sealant. The investigation on failure mechanism of the three parts carries critical meanings for improving reliability of LED production. This paper mainly focus on reliability and failure mechanism of the three kinds of phosphor and three kinds of sealant which are wildly used in high...
The trends for smartphone and other mobile devices are more than ever for integration and lower cost. Meanwhile, a higher degree of functionality and performance, thinner profile, and longer battery life are some of the additional market drivers seen in these devices. The implications of these market drivers on the packaging content of mobile devices including internet of things (IoT) and wearable...
MEMS devices are continuous evolving to achieve smaller size and lower cost with improved performance. The Through silicon via (TSV) technology offers a promising approach from the perspective of MEMS device packaging and integration. In this paper, we report our latest progress on wafer level packaging of MEMS devices by via-last process. The 200mm MEMS wafer was bonded with a glass cap wafer. Then,...
The emergence and evolution of any package technology is driven by market trends as experienced by the end application. With the maturation of the mobile market, the trends for Smartphone and other mobile devices are more than ever for lower cost. Meanwhile, a higher degree of functionality and performance, thinner profile, and longer battery life are some of the additional market drivers seen in...
This paper proposes a combination of annular copper and cylindrical copper as the TSV conductor to decrease the effect of thermal mismatch between copper and silicon in MEMS packaging, which results in a reliability risk between redistribution layer (RDL) and TSV. There are three important factors which may have the most serious influence on the reliability being simulated and analyzed. They are the...
To overcome the severe challenges of achieving an extra-thin thickness down to 10 μm for chip stacking of 3D-IC module such as the mechanical damages appear at chip grinding, subsequent steps of wafer handling, and robust assembly, a novel pre-molding technology applied to assembled stacked module prior to chip thinning procedure is presented in this study. Packaging vehicle is fabricated to demonstrate...
The advancement of silicon scaling to 14/16 nanometer (nm) in support of higher performance, higher bandwidth and lower power consumption in portable and mobile devices is pushing the boundaries of emerging packaging technologies to smaller fan-out packaging designs with finer line/spacing as well as improved electrical performance and passive embedded technology capabilities. Advanced embedded Wafer...
Silicon interposer has emerged as a substrate of choice for integrating fine pitch, high density devices. Conventional packaging of 2.5D/3D devices involves multiple level of assemblies. Normally, 2.5D/3D devices are first assembled on thinned silicon interposer with aspect ratio of 10:100 followed by second level assembly on a multi-layer organic build-up substrate. In this study we introduce direct...
Three-dimensional integrated circuits (3D-ICs) packaging has attracted a lots of attentions due to it has advantages of integrating heterogeneous functions among stacked chips. The thermal mismatch stresses with regard to interconnects composed through silicon via (TSV) and microbump induced by thermal cycling loads becomes a serious concern while a thinner stacked die thickness is required. To shrink...
Through-silicon via (TSV) technology has been the core of the next generation of 3D integration. Although some TSV reliability issues have been addressed in some literatures, but the sidewall scallop resulted from Bosch etch process has not been thoroughly investigated. In this paper, we focus on the effects of different sidewall scallops on the interfacial stress evolution. An axi-symmetric single...
A low-cost and manufacturable 3D IC substrate-less Chip-on-Wafer (CoW) package has been studied. The new structure is a result of process simplification from the production-proven Chip on Wafer on Substrate (CoWoS™) technology. It features three layers of submicron (0.8µm pitch) Cu RDL on a Si interposer. High interposer yield is ensured with the excellent FAB-grade low defect density as demonstrated...
Through-silicon via (TSV) technology has been the core of the next generation of 3D integration. Although some TSV reliability issues have been addressed in some literatures, but the sidewall scallop resulted from Bosch etch process has not been thoroughly investigated. In this paper, we focus on the effects of different sidewall scallops on the interfacial stress evolution. An axi-symmetric single...
This paper introduces a new encapsulated WLCSP product (eWLCS). The new product has a thin protective coating applied to all exposed silicon surfaces on the die. The applied coating protects the silicon and fragile dielectrics and prevents handling damage during dicing and assembly operations, effectively providing a durable packaged part in the form factor of a WLCSP. The manufacturing process leverages...
Conjunction of silicon crystals with surface over 10 cm² with molybdenum discs by means of silver paste sintering is being discussed. It is shown that to ensure strength of joint and low thermomechanical stress selection of dependencies of pressure and temperature on time is very important. It is necessary to ensure thermal stability of multilayer metal process on jointed surfaces. Experimental elements...
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