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On advanced technology nodes, increases in power density, non-planar architectures and different material systems can exacerbate local self-heating due to active power dissipation, which can affect device performance and reliability in various ways. This paper presents an overview of the research on self-heating in transistors and discusses modulators, measurement schemes, spatio-temporal sensitivities,...
This last decade Silicon-on-Insulator (SOI) MOSFET technology has demonstrated its potentialities for high frequency commercial applications pushing the limits of CMOS technology. Thanks to the thinning down of the silicon channel, SOI MOSFETs operate in fully depleted regime and short channel effects are under controlled. Besides the gate length downscaling, strain channel engineering is introduced...
State of the art 2D and 3D electro-thermal particle-based device simulators have been developed to investigate degradation in the on-current due to self-heating effects in fully-depleted SOI devices and nanowire transistors. For the fully-depleted SOI devices in which we have thin silicon slabs temperature and thickness dependent expression for the thermal conductivity data that agrees perfectly with...
We report on the development of metallic source and drain module for FDSOI MOSFETs including lateral salicidation of the channel edges and dopant segregation technique. Metal barrier type (TiN or Ti/TiN), optimized doping conditions, controlled PtSi penetration below spacers and suitable cleaning of the silicide surface lead to very low specific contact resistivity values (down to 0.1 Ωμm2). We thus...
We investigate the influence of different technological parameters on ESD robustness in advanced FDSOI devices. From Transmission Line Pulse (TLP) measurements, a comparison with other technologies enables us to evaluate the impact of ultrathin film and buried oxide. A solution based on hybrid SOI/bulk co-integration by using Silicon-On-Nothing technology is presented in order to improve ultra-thin...
In this paper we present simulation results obtained with our electro-thermal device simulator when modeling different technology generations of FD-SOI devices. In particular, we stress out the importance of the temperature boundary conditions for digital and analog circuits and the use of the full model which takes into account both temperature and thickness dependence (which is particularly important...
This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip...
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