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In this paper, a new methodology for analysis of SSO effect on jitter value based on IBIS v5.0 is proposed. Subsequently, investigation of the impact of simultaneous switching output (SSO) noise, jitter and timing closure of a complete 8 bit LPDDR2 bus at 400 MHz obtained using this developed methodology is presented. Experimental results obtained on automotive microcontrollers using the developed...
This paper discusses the challenges in system level timing closure of a high speed DDR interface. The different aspects of the DDR controller, I/O buffer, package and board to be modeled for ensuring stable operation at the targeted speed are described.
This paper discusses the challenges in system level timing closure of a high speed DDR interface. The different aspects of the DDR controller, I/O buffer, package and board to be modeled for ensuring stable operation at the targeted speed are described.
With shrinking geometries and increasing complexity of the designs, the use of SPICE simulator (SPICE) is a must to perform accurate timing analysis of the critical paths. This also improves the signoff confidence of the design. However, in this process designers may discover a miscorrelation between static timing analysis (STA) and SPICE. There are articles that provide in-depth descriptions of STA-SPICE...
In this paper, we propose a statistical model to analyze the crosstalk noise induced by process variations on single-walled carbon nanotube (SWCNT). Our approach is based on a closed-form metric, which simplifies the noise peak voltage of SWCNT buses into a linear function of process variations. The methodology is based on an assumption that if the variational parameters are independent Gaussian variables,...
Wave pipelining has gained attention for NoC interconnect by its promise of high bandwidth using simple circuits. Reliability issues must be addressed before wave pipelining can be used in practice; so, we develop a statistical model of dynamic timing uncertainty. We show that it is important to distinguish between static and dynamic sources of timing uncertainty, because source-synchronous wave pipelining...
Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and significant parametric variations. Asynchronous circuits have the great potential to achieve delay insensitive, high performance and low power nanoelectronic design, while the existing asynchronous circuits do not guarantee logic and timing...
Simultaneous switching noise (SSN) is an important issue for the design and test and actual ICs. In particular, SSN that originates from the internal logic circuitry becomes a serious problem as the speed and density of the internal circuit increase. In this paper, an on-chip monitor is proposed to detect potential logic errors in digital circuits due to the presence of SSN. This monitor checks the...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
This paper proposes a new approach to analyze crosstalk of coupled interconnects in the presence of process variations. The suggested method translates correlated process variations into orthogonal random variables by principle component analysis (PCA). combined with polynomial chaos expression (PCE), the technique utilizes Stochastic Collocation Method (SCM) to analyze the system response of coupled...
For several decades, the output from semiconductor manufacturers has been high volume products with process optimisation being continued throughout the lifetime of the product to ensure a satisfactory yield. However, product lifetimes are continually shrinking to keep pace with market demands. Furthermore there is an increase in dasiafoundrypsila business where product volumes are low; consequently...
A novel methodology for accurate and efficient static timing analysis is presented in this paper. The methodology is based on finding a frequency domain model for the gates which allows uniform treatment of the gates and interconnects. It is shown that despite the highly nonlinear overall gate model, a frequency domain model of the gate with the model parameters, gate moments, as functions of the...
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