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An all-digital de-skew clock generator for arbitrary wide range delay is proposed to minimize the instability of the clock settling while achieving fast locking time. The clock skew problem is detrimental in high-speed applications, especially when the skew is longer than multi-cycles. The proposed clock generator was fabricated in a 0.18-μm CMOS technology. The clock generator achieves a measured...
A low-jitter 300- to 800-MHz de-skew clock generator for arbitrary wide range delay is proposed to minimize the instability of the clock settling while maintaining a wide loop bandwidth. The clock skew problem is detrimental in the high speed applications, especially when the skew is longer than multi-cycles. The proposed generator was fabricated in a 0.18-μm CMOS process. The clock generator...
A 2 ?? 25 Gb/s deserializer for 100 Gb/s Ethernet is implemented in 65 nm CMOS technology. Employing regulated limiting amplifiers, full-rate CDRs, a built-in clock generator, and a 2:5 DMUX, this two-channel prototype achieves BER < 10-12 with 20 mVpp input sensitivity while consuming a total power of 510 mW.
Influence of intersymbol interference value on eye diagram on duration opening and dependence of number of generators of network elements in a circuit of clock network synchronization from dispersion relative value changing is considered.
An all-digital clock generator for dynamic frequency scaling is presented by using a cyclic clock multiplier. It realizes the fractional or multiplied output clock within four reference clock cycles. The frequency of the output clock can be programmed as Mfref/N (fref is the reference clock frequency, 1lesMles7, and 1lesNles8). It has been fabricated in a 0.18 um CMOS process. The measured rms jitter...
This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.
A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
A circuit for on-chip measurement of long-term jitter, period jitter, and clock skew, is demonstrated. The circuit uses a single latch and a voltage-controlled delay element, and is evaluated in a stand-alone pad frame. Excellent reproduction of jitter measured by oscilloscope is shown. Measured jitter resolution is 1 ps or better. The circuit is also incorporated into a 2 GHz clock distribution network...
We designed and built a novel all-optical re-timing, re-amplifying, and re-shaping (3R) regeneration system based on terahertz optical asymmetric demultiplexers (TOADs) developed in our laboratory. The system is capable of parallel processing multiple wavelengths, a feature which will significantly improve the scalability of current wavelength division multiplexing (WDM) networks. Performance against...
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