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A multiphase all-digital delay-locked loop (DLL) with reuse SAR has been designed with TSMC 0.18μm CMOS technology. The proposed reuse successive approximation register (Reuse SAR) reduces the hardware cost effectively as compared with a conventional SAR or a two-stage SAR. The digital to voltage convertor has six coarse controlled bits and six fine controlled bits to adjust voltage for voltage controlled...
This paper presents an area-efficient temperature sensor with 1°C resolution based on a successive approximation algorithm. SoC requires several die temperature sensors to be integrated in a chip to manage the performance because die temperature directly affects leakage current level and performance of clock-based digital circuits. However, the size of temperatures sensor restricts the use of sensor...
A delay-locked loop (DLL) with digital background calibration is presented. The static phase error of a DLL may exist owing to the current mismatch in the charge pump (CP). A digital background calibration using the time amplifier is presented. This DLL is fabricated in a CMOS 0.18 ??m technology. The measured input frequency range of this DLL is from 400 MHz to 525 MHz. The measured static phase...
This article presents a power-efficient and low- voltage CMOS output driver circuit based on low-voltage differential signaling (LVDS) standard. To reduce the ringing at the output of the proposed driver circuit and simultaneously keep the power consumption low, a new technique has been applied to control the output voltage slew. A pre-driver circuit is also utilized to have a very low total equivalent...
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