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In this paper, a new methodology for analysis of SSO effect on jitter value based on IBIS v5.0 is proposed. Subsequently, investigation of the impact of simultaneous switching output (SSO) noise, jitter and timing closure of a complete 8 bit LPDDR2 bus at 400 MHz obtained using this developed methodology is presented. Experimental results obtained on automotive microcontrollers using the developed...
To improve power efficiency, a power saving technique for the ring-type DC-DC converter is proposed in this paper. By reusing a part of the electric charge in stray parasitic capacitances, the proposed converter can achieve higher power efficiency than the conventional converter. The results of the simulation program with integrated circuit emphasis (SPICE) simulation showed that more than 8% of the...
We abstract the I/O functionality of continuous-time dynamical systems (e.g., SPICE netlists with combinational and sequential logic) as Finite State Machines (FSMs). This enables efficient simulation of large designs implemented with less-than-perfect devices and components, and also opens the door to formal verification of transistor-level designs against higher-level specifications. In particular,...
This paper presents a novel switching scheme for an ultra-low energy charge-redistribution digital-to-analog converter (DAC) to be used in successive-approximation register (SAR) analog-to-digital converter (ADC). The proposed scheme employs unit capacitors for voltage sampling and charge redistribution. Compared with previously published capacitive DAC which uses the same unit size of capacitor array,...
This paper proposes first-order and third-order Switched Capacitor realizations of fractional order differentiators and integrators. First, the s-to-z transformation is expanded for fractional powers using Taylor series expansion (TSE) and continued fraction expansion (CFE). Then, the stabilized models of the fractional order differentiators and integrators are realized using Switched capacitor (SC)...
This paper presents a new method to recover energy in an Analog-to-Digital Converter (ADC) based on the principle of adiabatic charging. The ADC comprises an Adiabatic Charging Charge Redistribution (ACCR) DAC, a dynamic comparator, and a Successive-Approximation-Register (SAR) counter. Charges in the ACCR DAC can be recovered through a resonant power supply and adiabatic switch. These charges can...
This paper presents a design of a high-performance sample-and-hold (S/H) circuit. Switches' constraints on signal settling in charge-transferring S/H circuit are discussed. Then the optimum combination of switches for this S/H circuit is proposed. Hspice simulated results based on Chartered 0.18μ 1P5M CMOS process under 1.8V supply voltage shows a 103dB SFDR, 86dB SNDR at Nyquist input @ Fs=125MS/s...
A new clock feed-through compensation configuration and corresponding bootstrapped switch are presented and designed optimally with UMC Mixed-Mode/RF 0.18 ??m 1P6M P-Sub Twin-Well CMOS process by orientating and elaborate designing the switch MOSFETs that have influence on the delay path match of the clock boosting circuit. HSPICE simulation results show that the proposed clock feed-through compensation...
Reducing leakage dissipation is becoming more and more important in low-power design. The dynamic energy dissipation reduction of adiabatic circuits using power-gating schemes has been introduced. In order to reduce leakage losses of the adiabatic circuits using power-gating schemes under deep submicron process, this paper proposes a MTCMOS (Multi-Threshold CMOS) power-gating scheme for adiabatic...
This paper presents the implementations of adiabatic flip-flops and sequential circuits using single-phase power-clock with power-gating scheme. All circuits are realized by using the improved single-phase CAL (clocked adiabatic logic) technology. A power-gating scheme for the improved CAL circuits is used to reduce energy dissipation in sleep mode. All circuits are implemented using Chartered 0.35...
This work uses switch-level Verilog to simulate entire benchmarks using transistor level schematics and post-layout capacitance extraction. By translating a schematic netlist into a transistor level Verilog netlist, thousands of benchmark cycles can be simulated in minutes or hours compared with only tens of cycles using a fast spice simulator. This difference in simulation speed enables simulating...
Loss of reference clock may harm the functionality of system on chips (SoCs) permanently or intermittently. In this paper, we propose a novel circuit based on an XOR phase detector and a simple charge pump to monitor the input reference clock continuously. This circuit can provide a signal to indicate the loss of reference clock. SPICE simulation results confirm that the proposed reference clock detect...
Adiabatic logic is also called energy recovery logic. Thermodynamic meaning no heat transfer. Instead of dissipating power reuse it. It achieves low power consumption by restricting the currents to flow across devices with low voltage drop and by recycling the energy stored in their node capacitors using an AC type power supply rather than DC. This paper focuses on principles of adiabatic logic, its...
In this paper, a modified auto zeroed integrator is used to design and simulate a low-voltage high-speed and accurate switched capacitor pseudo 2-path filter. The filter is a sixth-order Chebyshev band-pass filter operating at sampling frequency of 1MHz and center frequency of 250 kHz with a quality factor of 50. The circuit is simulated using HSPICE and 0.25??m CMOS technology.
A current-based close loop track-and-hold circuit with a speed of 50 MS/s and 8-bit resolution for plusmn0.8 V input range is implemented using a voltage-control current source and a current switch. The proposed circuit has the advantage of high input impedance and stable output. SPICE simulation using 0.35 mum SMIC CMOS technology with plusmn1.65 V supply showed that the proposed track-and-hold circuit...
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend...
This paper describes a design flow for the circuit-level optimization of a technology. The concurrent exploration of device characteristics and library design choices leads to a more application-optimal technology. We illustrate the design flow by: 1) analyzing the impact of buffer cell design, and 2) by optimizing a 130 nm technology for low operational power.
Driven by the proliferation of implantable and self-powered electronic devices, low-voltage, low-power, high-efficiency DC-DC power converters are on high demands. This paper first reviews the state-of-the-arts charge pumps, with focus on power loss minimization, power stage architectures and control signaling. A new four-phase complimentary charge pump is then proposed. By employing the techniques...
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