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We present an aging analysis flow able to calculate the degraded circuit timing. To the best of our knowledge it is the first approach on gate level so far capable of analyzing the impact of the two dominant drift-related aging effects - NBTI and HCI - on complex digital circuits. The aging-aware gate model used to compute the aged circuit timing provides not just the cell delay degradation, but also...
This work establishes an analytical model framework to account for the NBTI aging effect on statistical circuit delay distribution. In this paper, we explain how circuit NBTI mitigation techniques can account for this extra variability and further present the impact of statistical PMOS NBTI DC-lifetime variability on the product delay spread.
Many-core scaling now faces a power wall. The gap between the number of cores that fit on a die and the number that can operate simultaneously under the power budget is rapidly increasing with technology scaling. In future designs, many of the cores may have to be dormant at any given time to meet the power budget. To push back the many-core power wall, this paper proposes Dynamic Voltage Scaling...
Stress sensing test chips are widely utilized to investigate integrated circuit die stresses arising from assembly and packaging operations. In order to utilize these test chips to measure stresses over a wide range of temperatures, one must have values of six piezoresistive coefficients for n- and p-type silicon over the temperature range of interest. However, the literature provides limited data...
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