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In 3-D interconnect structures, process-induced thermal stresses around through-silicon-vias (TSVs) raise serious reliability issues such as Si cracking and performance degradation of devices. In this study, the thermo-mechanical reliability of 3-D interconnect was investigated using finite element analysis (FEA) combined with analytical methods. FEA simulation demonstrated that the thermal stresses...
More and more dense packaging is one of the most important challenges in advanced electronics and micro technology, driven by requirements like low cost and high reliability. One way to meet these demands is to follow the so-called ldquochip in duromerrdquo approach, which allows an extremely dense integration and very short interconnects. Already in the very first design phase of advanced products,...
In this paper the reliability of the isolation substrate and chip mountdown solder interconnect of power modules under thermal-mechanical loading has been analysed using a numerical modelling approach. The damage indicators such as the peel stress and the accumulated plastic work density in solder interconnect are calculated for a range of geometrical design parameters, and the effects of these parameters...
In this study, a new packaging technology, chip-on-metal (COM) panel level package (PLP), is proposed to resolve the problem of assembling a fine-pitched chip to a coarse-pitched substrate. During the manufacturing process, the filler polymer material is selected to fill the trench around the chip and provide a smooth surface for the redistribution lines. Therefore, the solder bumps could be located...
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