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Dual-edge-triggered (DET) synchronous operation is a very attractive option for low-power, high-performance designs. Compared to conventional single-edge synchronous systems, DET operation is capable of providing the same throughput at half the clock frequency. This can lead to significant power savings on the clock network that is often one of the major contributors to total system power. However,...
The significant PVT variations seen with modern technologies make synchronous design inefficient. Asynchronous design with its flexible timing is a promising alternative, but prototyping is difficult on the available FPGA platforms which are clock centric and do not provide the required functional primitives like mutual exclusion or Muller C-elements. The solutions proposed in the literature work...
In this paper, a novel circuit topology is presented for Clock gating cell in which the basic parts (gater and latch) are realized with transmission gate. The simple structure and small amount of leakage power make this topology suitable for ultra-low power designs in sub/near-threshold regions. Circuit simulations and Post-Synthesis simulation results of a simple Clock gated ITC'99 benchmark circuit...
Many disturbances in the electronic systems are caused by the space radiations. Like other electronic systems, the electronic systems are subject to improve to nanoelectronic systems. Quantum Cellular Automata (QCA) represents an emerging technology at the nanotechnology level. The effects of space radiations in QCA inverter gate are investigated in this paper. Single Electron Fault (SEF) is a fault...
The paper presents the implementation of ultra low power 8 bit carry look ahead adder circuit operated by single-phase adiabatic dynamic logic (SPADL) which, unlike any other existing adiabatic logic family, uses single sinusoidal supply-clock. This not only ensures higher energy efficiency, but also simplifies the clock design which would be otherwise more complicated due to the signal synchronization...
In the literature, quasi-delay-insensitive (QDI) asynchronous circuits utilizing Pre-Charge Half Buffers (PCHB) are based on either dynamic or semi-static implementations. In this paper, a static implementation of PCHB is presented, and compared to previous PCHB architectures and static NULL Convention Logic (NCL), using a full adder design. Transistor level simulation shows that the static PCHB architecture...
Quantum Cellular Automata (QCA) represents an emerging technology at the nanotechnology level. There are various faults which may occur in QCA cells. One of these faults is the Single Electron Fault (SEF) that can happen during manufacturing or operation of QCA circuits. A detailed simulation based logic level modeling of Single Electron Fault for QCA Inverter gate is represented in this paper.
In this paper we present a novel ultra-low-voltage (ULV) CMOS flip-flop. The ULV flip-flop offers increased speed compared to other FF's for low supply voltages. The pulse generator (PG) circuit in a conventional sense amplifier SAFF is replaced by a high-speed tristate edge generator (EG) with a rise- and fall-time less than 1/10 of an inverter operating with the same supply voltage. In essence the...
This paper presents fault modeling and analysis for resistive bridging defects in a synchronizer constructed with two D flip-flops. Bridging defects are exhaustively injected into any two nodes of the synchronizer to find all possible faults that might occur in the synchronizer, and HSPICE is used to perform circuit analysis.
In this paper we examine a quasi static and a static ultra low-voltage precharge CMOS logic. The static ultra low-voltage logic can be used to design high speed and energy efficient CMOS circuits. Using the proposed circuit technique the static current consumption can controlled and the logic style is suitable for large logic depth, i.e. serial adders. The delay of a static ultra low-voltage gate...
This paper presents fault modeling and analysis for open defects in a synchronizer that is implemented by two D flip-flops. Open defects are injected into any node of the synchronizer, and HSPICE is used to perform circuit analysis. The major purpose of this analysis is to find all possible faults that might occur in the synchronizer by open defects. The results obtained can be used to develop methods...
This paper presents fault modeling and analysis for bridging defects in a synchronizer that is implemented by two D flip-flops. Bridging defects are injected into any two nodes of the syncronizer, and HSPICE is used to perform circuit analysis. The defects are exhaustively injected and simulated to find all possible faults that might occur in the synchronizer. The results obtained can be used to develop...
This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
A circuit for on-chip measurement of long-term jitter, period jitter, and clock skew, is demonstrated. The circuit uses a single latch and a voltage-controlled delay element, and is evaluated in a stand-alone pad frame. Excellent reproduction of jitter measured by oscilloscope is shown. Measured jitter resolution is 1 ps or better. The circuit is also incorporated into a 2 GHz clock distribution network...
This paper proposes an improved synchronization control scheme of a low cost 400 Hz power supply for no-break power transfer. In the case of aircraft application, the 400 Hz power supply called as ground power units (GPU) has been accepted as external electrical power system during stopovers in ground. When transferring from one power source to the other, there is a momentary break in supply. To transfer...
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