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Design and analysis of two high-speed high dynamic-range track-and-hold amplifiers are presented in this paper using 65- and 90-nm CMOS processes. To achieve remarkable circuit performance in the advanced CMOS regime, the cascode topology with an inductive peaking technique and the distributed topology are employed in the track-and-hold amplifiers. The circuit topology is investigated to obtain the...
Bootstrapping techniques improve the linearity of switched-capacitor circuits, especially for low supply voltage. This paper proposes simple but effective techniques for bootstrapping floating switches. The method is applicable to such fundamental circuits as sample-and-hold (S/H) stages, switched-capacitor (SC) filters and SC amplifiers. It can make the onresistance and channel charge of the switches...
This paper introduces new charge and discharge paths to speed up the turn-on and turn-off process of bootstrapped switch. In the mean time, linearity is improved without increasing capacitance or area. The proposed switch is designed in SMIC 65nm CMOS process and the results indicate that total harmonic distortion (THD) of 95dB is acquired when 103MHz input signal is sampled at 1Gsps.
This paper describes a 180 nm CMOS thin film SOI technology developed for RF switch applications. For the first time we show that the well-known harmonic generation issue in HRES SOI technologies can be suppressed with one additional mask. Power handling, linearity, and Ron*Coff product are competitive with GaAs pHEMT and silicon-on-sapphire technologies.
An on-chip buck converter with 3D chip stacking is proposed and the operation is experimentally verified. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz and a 2x2mm on-chip LC output filter in 0.35mum CMOS. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3%, and the power efficiency...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
In this paper, a CMOS analog-to-digital converter (ADC) for Ultra Wide Band (UWB) applications with a 6-bit 1GSPS at 1.8 V is described. The architecture of the proposed ADC is based on a fully folded ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) is proposed. Further,...
A high power SPDT antenna switch is designed and implemented using a standard 0.18um CMOS process. Multi-stack FETs structure with feed-forward capacitors in a Rx switch were chosen to achieve high power-handling capability of a Tx switch. Allowance of the negative voltage swing at either a source port or a drain port is ensured by applying the resistive body floating technique to the each switch...
We have systematically studied the microwave noise, power, and linearity characteristics of field-plate (FP) 0.13-mum CMOS transistors in which the field-plate are separately connected to the gate and source terminals. The gate-terminated FP NMOS (FP-G NMOS) provided the best minimum noise figure (NFmin) at 6 GHz compared to standard device and source- terminated FP device (FP-S NMOS) owing to the...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
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