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The mechanical performance (stress-strain behavior and creep curve) of joints bonded with pressure-sensitive adhesives (PSAs) are complex due to the multiple phases of morphological evolution of the adhesive layer under uniaxial tensile loading. PSAs are widely used in field applications because of their benign processing conditions, low price, and various available laminated configurations, most...
The focus of this paper is on a modeling methodology for capturing the complex mechanical behavior of a single layer pressure-sensitive adhesive (PSA) system, based on empirical observations of its stress-strain behavior. This study is motivated by the fact that there is very limited modeling ability to mechanistically predict the bimodal stress-strain curves of single-layer PSAs. Empirical observations...
One-shot micro-valves are key to applications that require leak-proof sealing of micro-cavities before they are irreversibly triggered to expose the cavity content to the outside environment. Here, we report a novel micro-scale one-shot valve made of graphene transferred on to silicon-nitride (SixNy) membranes. The valve triggers thermo-mechanically in 15.4±3.9 msec consuming 142.1±13.5 mW electrical...
A new additive ultra-thin chip fabrication process is presented, utilizing an array of vertical anchors that mechanically connect silicon membrane chips to a standard silicon wafer. The process is demonstrated down to 8 μm silicon chip thickness, with a chip thickness control better than ±0.2 μm and a surface topography with average roughness <; 7 nm. Such pre-processed wafers can be used for CMOS...
We examine the thermomechanical tradeoffs in a novel technology for high density interconnect (HDI) substrates. Fabricated from silicon (Si) wafers with planar cavities of highly-filled composite encapsulant, the technology leverages established Si photolithography but offers improved mechanical properties. Modules are subject to thermomechanical stress during encapsulant cure, assembly reflow, module...
Ultra-thin chip technology is identified as an enabler for overcoming bottlenecks in microelectronics, such as 3D integration, and for leading to new applications, such as hybrid, flexible system-in-foil (SiF). This, however, calls for new techniques in fabricating very thin wafers or chips, in applying them to device integration processes and in assembly and packaging. The application to SiF requires...
A new package structure based on printed circuit board (PCB) as carrier substrate was proposed, aiming at providing an implementation of system-in package (SiP) emphasizing small size and more importantly low cost. This structure is built upon a multilayer PCB, where open cavities are created in the top and bottom layers to house active dies, allowing package size reduction as well as protection against...
Plastic electronics, thin-film-transistors on foil and ultra-thin chips on foil are technologies currently pursued to support the strongly emerging market for flexible electronics. Ultra-thin CMOS chips in such systems will provide solutions whenever high circuit performance and/or complexity are required. Ultra-thin Si chips (6 to 20 mum) are fabricated by using a recently introduced technology based...
The effect of thinning down the chip thickness, will affect the stress pattern in the chip and causes the chip to deform locally when the thickness of the chip is thinner than a certain critical value. Such a local deformation may cause sharp gradient of residual stress around the solder bumps and thus, various failures. This paper shows that by considering the effect of solder bumps on a 50 mum chip,...
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