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An ultra low voltage rail-to-rail DTMOS voltage follower is presented. The circuit is developed based on a complementary source follower with a common-source output stage. The circuit is designed using a 0.13 μm CMOS technology and SPICE is used to verify the circuit performance. The voltage follower can drive ± 0.25 V to the 500 Ω with the total harmonic distortion (THD) of 0.4% at the operating...
This paper introduces Spicedim, a graphical programming interface for integrated CMOS circuit design. It connects the SPICE netlist level to an easy to use programming language, both combined in a graphical development environment. After classifying the context of this tool the fundamental application for parametric circuit simulation and signal processing is shown. This is done at the example of...
This paper presents a design of a high-performance sample-and-hold (S/H) circuit. Switches' constraints on signal settling in charge-transferring S/H circuit are discussed. Then the optimum combination of switches for this S/H circuit is proposed. Hspice simulated results based on Chartered 0.18μ 1P5M CMOS process under 1.8V supply voltage shows a 103dB SFDR, 86dB SNDR at Nyquist input @ Fs=125MS/s...
Power consumption is now a major technical problem facing the CMOS circuits in deep submicron process. As process moves to finer technologies, leakage power significantly increases very rapidly due to the high transistor density, reduced voltage and oxide thickness. We first experimentally investigate existing low-power techniques and point out problems with them. We then propose a family of circuit...
A novel low-power and high-performance Standard Ternary Inverter (STI) for CMOS technology is proposed in this paper. This inverter could be used as a fundamental block for designing other ternary basic logic gates. This circuit consists of only MOS transistors and capacitors without any area consuming resistors in its structure. Another great advantage of this design in comparison with the other...
In this paper, a new current-mode (CM) single-input-three-output (SITO) universal filter based on single current-controlled current follower transconductance amplifier (CCCFTA) as active element and two capacitors, is presented. The proposed filter enables to realize all standard filter functions. Moreover, by expanding the CM filter via CCCFTA-based negative resistor, the CM quadrature oscillator...
This paper presents design of the integrated chaotic neuron using 0.8 ??m single poly CMOS technology, its dynamical behavior analysis. Proposed chaotic neuron consists of several op-amps, sample and hold circuits, a nonlinear function block for chaotic signal generation, a two-phase clock circuits and sigmoid output function block. From HSPICE simulation results of the circuit, approximated empirical...
In this paper, we propose a new complementary image sensor pixel structure by improving the conventional 3TR pixel structure. Proposed complementary pixel structure for wide dynamic range CIS consists of photo diode, PMOS reset transistor, several PMOS and NMOS transistors for complementary signals. We show SPICE simulation results of the complementary image pixel structure for optimization. Proposed...
As CMOS technology continues to scale, the accurate prediction of silicon timing through the use of pre-silicon modeling and analysis has become especially difficult. These timing mismatches are important because they make it hard to accurately design circuits that meet timing specifications at first-silicon. Among all the parameters leading to the timing discrepancy between simulation and silicon,...
Probabilistic CMOS is considered a promising technology for future generations of computing devices. By embracing possibly incorrect calculations, the technology makes it possible to trade correctness of circuit operations for potentially significant energy saving. For systematic design of probabilistic circuits, accurate mathematical models are indispensable. To this end, we propose a model of probabilistic...
A CDTA (Current Differencing Transconductance Amplifier)-based quadrature oscillator circuit is proposed, employing two CDTAs and two capacitors. All capacitors are grounded. No oscillation condition is needed for the proposed oscillator circuit. The output terminals of the oscillator circuit exhibit high output impedance values, high-end features without any need to a buffer circuit for proper drive...
This paper deals with using MO-TRIBES, an adaptive multiobjective particle swarm optimization algorithm, for optimally sizing CMOS positive second generation current conveyors. Pareto front is generated while minimizing parasitic X-port input resistance RX and maximizing current high cut-off frequency fchi. Results obtained using MO-TRIBES are provided and compared to those obtained using the classical...
A new clock feed-through compensation configuration and corresponding bootstrapped switch are presented and designed optimally with UMC Mixed-Mode/RF 0.18 ??m 1P6M P-Sub Twin-Well CMOS process by orientating and elaborate designing the switch MOSFETs that have influence on the delay path match of the clock boosting circuit. HSPICE simulation results show that the proposed clock feed-through compensation...
This paper discusses general procedures for simulation, design optimization, measurement and modeling of accurate and scalable on-chip RF spiral inductors in standard foundry CMOS for industrial applications. Electro-magnetic (EM) solver is used to simulate and optimize design of a library of inductors with various dimensions and specifications aiming to provide accurate and scalable inductors for...
A window-comparator CMOS oscillator with slope compensation ability, which can be applied in DC-DC converter control IC, is presented in this paper. And the slope compensation circuit, simple and effective, simplifies the whole circuit. Using 0.35 mum CMOS model, the oscillator is simulated by Hspice, and the result indicates that the frequency of the output of the oscillator is stable at 1.2 MHz...
As the size of CMOS devices is approaching the atomic level, the increasing intrinsic device variability is leading to higher failure rates in conventional CMOS designs. This paper introduces a design tool capable of evolving CMOS topologies using a modified form of Cartesian genetic programming and a multi-objective strategy. The effect of intrinsic variability within the design is then analysed...
Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and significant parametric variations. Asynchronous circuits have the great potential to achieve delay insensitive, high performance and low power nanoelectronic design, while the existing asynchronous circuits do not guarantee logic and timing...
Finite element device level simulations were used in conjunction with SPICE modeling to design and optimize a complementary MOS inverter circuit with an organic p-type and an inorganic n-type transistor combination. The device characteristics of the p-type and the n-type transistors were generated through 2D finite element device level simulations. The drain current (ID) vs. drain-source voltage (V...
In the advanced Low Power (LP) CMOS technology nodes gate-to-source/drain overlap capacitance (COV), gate-to-contact capacitance (CCO) and gate sidewall fringe capacitance (Cf) have become increasingly important component(s) of transistor parasitic. Accurate extraction and modeling of these parasitic are essential in accurate estimation of circuit performance. In this paper we describe test structure...
A new high precision superior-order curvature-corrected integrated nanostructure will be presented. In order to improve the temperature behavior of the circuit, a double differential structure will be used, implementing the linear and the superior-order curvature corrections. An original CTAT (complementary to absolute temperature) voltage generator will be proposed, using exclusively MOS transistors...
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