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A 1.2V 10bit 83MS/s pipeline ADC implemented in 130nm CMOS Technology is described with practical design techniques and considerations. Emphasis was placed on noise analysis and capacitance optimization, which helps to reduce both die area and power consumption. Design experiences of operational amplifier, comparator and switches were also shared. This design achieves INL and DNL of +0.65/-0.53LSB...
A new switch control method for a capacitive DAC architecture has been presented. This has been implemented to make a successive approximation register (SAR) ADC more energy efficient. By splitting the capacitor array into two equal halves and using a unity gain buffer, the proposed architecture reduces the switching energy by 97 percent compared to the conventional switching method. The proposed...
In this paper a 4-bit expandable algorithmic Analog-to-Digital Converter has been implemented. It is based on current mode technique. The Analog-to-Digital Converter has been implemented for 4-bits here but can be easily expanded for higher number of bits using the algorithm presented here. The converter uses a current comparator. We have simulated two popular structures of current comparators that...
This paper presents the performance evolution over time for monolithic ADC implementations reported in scientific publications. The survey is based on an exhaustive search of IEEE journals and conferences central to the field from 1974 to 2010 and thus represents a near-exhaustive survey of reported scientific ADC data. Based on the full set of historical data, empirically observed evolution trends...
In this paper, the trade-off between device mismatch, quantization noise and device noise in successive approximation register analog to digital converter (SAR ADC) is investigated. An optimization method for designing area-constrained SAR ADC with highest possible energy efficiency for a given dynamic range (DR) is proposed. By taking device noise and process mismatch information into account, it...
This paper presents the design methodology to recover charges in Analog-to-Digital Converter using adiabatic technique. Charge redistribution Successive Approximation Register (SAR) ADC is used as the main ADC architecture. The proposed ADC can operate in two modes - fast switching mode and adiabatic mode. In the fast switching mode, conventional DC supply is used and the ADC performs normal SAR ADC...
This paper proposes 4-bit, 1.8V Flash Analog to Digital Converter (ADC) design using CMOS-LTE (CMOS Linear Tunable Transconductance Element) Comparator with 500nm technology. Reference voltages are generated by systematically sizing the transistors of the comparators, thus completely eliminating the resistive ladder network required for the architecture. The PSRR (Power Supply Rejection Ratio) results...
This paper presents an ultra-low power voltage regulator used for low power wireless sensor nodes. As the input conditions for these types of regulators can be quite different in terms of voltage range and transient speed, the introduced architecture is designed to be almost insensitive to these variations. Even if the pass device is formed by an NMOS transistor, low-dropout operation is possible...
This paper presents a new method to recover energy in an Analog-to-Digital Converter (ADC) based on the principle of adiabatic charging. The ADC comprises an Adiabatic Charging Charge Redistribution (ACCR) DAC, a dynamic comparator, and a Successive-Approximation-Register (SAR) counter. Charges in the ACCR DAC can be recovered through a resonant power supply and adiabatic switch. These charges can...
The influence of CMOS scaling on A/D-converter performance is investigated by observing the entire body of experimental CMOS ADCs reported in IEEE journals and conferences central to the field from 1976 to 2010. Based on the near-exhaustive set of scientific data, empirically observed scaling trends are derived for performance in terms of noisefloor, speed and resolution, as well as for power efficiency...
A compact automatic gain control (AGC) loop for GNSS RF receiver is presented in this paper. The proposed AGC loop circuit achieves higher integration and lower power by eliminating the bulky off-chip capacitor and charge pump circuit, which are widely used in traditional AGC. The proposed AGC consists of a programmable gain amplifier (PGA), a 2-bit flash analog to digital converter (ADC), and a novel...
This paper presents a conditional capacitor averaging technique to enhance the linearity of 2.5-bit/stage high-resolution pipelined ADCs with capacitor mismatch. Design concepts of capacitor averaging and sorting techniques are employed to mitigate the error effect of capacitor mismatch. Moreover, the sorted capacitors and digital-to-digital converter (DAC) voltages in a 2.5-bit multiplying analog-to-digital...
A 14bit MDAC with 120MS/s conversion rate, in 0.35um CMOS technology is presented. The MDAC consumes a power of 36mW from a 3.3v power supply and its settling time is 7ns. It utilizes a new high speed, high gain Op Amp, with 102dB gain, and 1.2GHz bandwidth. The phase margin of Op Amp is 51° and its settling time is 5ns for feedback gain of 8. The Op Amp has a good linearity of -60dB.
A design of a 3.5 + 1-bit multiplying digital-to-analog converter (MDAC) which can be used in the first stage of a 14-bit 100MS/s pipelined analog-to-digital converter (ADC) is presented in this paper. Two decision levels are added in the MDAC so that bi-directional overflow of the input signal can be detected. Bootstrap structure with a buffer is proposed to prevent the large bootstrap capacitance...
This paper describes the implementation of a 14-bit pipelined analog-to-digital converter (ADC) operating at a sampling frequency of 50MS/s with an effective resolution of 11.1 bit at Nyquist rate, fabricated in a 130-nm technology with a supply voltage of 1.2 volts and a power consumption of less than 110 mW. The ADC consists of differently scaled 1.5-bit pipeline stages only and dispenses with the...
A signal-agnostic compressed sensing (CS) acquisition system is presented that addresses both the energy and telemetry bandwidth constraints of wireless sensors. The CS system enables continuous data acquisition and compression that are suitable for a variety of biophysical signals. A hardware efficient realization of the CS sampling demonstrates data compression up to 40x on an EEG signal while maintaining...
Switched Capacitor circuits are pervasive in highly integrated, mixed signal applications. Switched capacitor circuits fill a critical role in analog/digital interfaces particularly highly integrated applications. This chapter describes the basic building blocks that comprise switched Capacitor circuits. These blocks are the sample-and-hold (S/H), gain stage. From these elements more complex circuits...
Based on the principle of Pipeline ADC, a 10-bit, 50-MS/s pipeline A/D converter is presented in this paper. Combining with bootstrap circuit and bottom-plate sampling technology, a high linearity on-chip sample-and-hold (S/H) is realized. This ADC is optimized for high static and dynamic performance applications in imaging and digital communications. It operates at 1.2 V power supply and achieves...
This paper presents a novel digital delay-locked loop (DDLL) dedicated to generate multiphase delayed clocks for the development of the multi-channel analog-to-digital converters (ADCs) and/or time-to-digital converters (TDCs). The DDLL consists of a digital delay chain using linear delay elements, a Bangbang phase detector, a Up/Down counter and a digital filter. The digital filter is utilized to...
A CMOS imager is presented which has the ability to perform localized compressive sensing on-chip. In-pixel convolutions of the sensed image with measurement matrices are computed in real time, and a proposed programmable two-dimensional scrambling technique guarantees the randomness of the coefficients used in successive observation. A power and area-efficient implementation architecture is presented...
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