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In this paper, a 3mW 0.004mm2 6-bit time-to-digital converter (TDC) is presented. By re-using a single delay cell and sampling flip-flop (FF), mismatch free operation is achieved. PVT variations are tracked and corrected by a digital frequency lock loop (DFLL). The proposed TDC is demonstrated in a digital fractional-N PLL for WiFi/4G radios. A 20-bit high dynamic range (DR) digital-to-analog converter...
One emerging trend of implementing phase locked loop (PLL) based frequency synthesizers is to leverage digital signal processing in the loop filtering for more flexibility, scalability and smaller silicon area. This paper examines the pros and cons of such digital-intensive PLL architecture, and discusses techniques to minimize its overhead in terms of implementation cost and performance degradation...
This study presents a 6-Gb/s clock and data recovery (CDR) for the high-speed data transmission systems. Similar to the concept of the oversampling CDR, the proposed CDR presents an alternative scheme, which uses the data delay window (DDW) and a sensing-amplified phase detector (SAPD) to substitute the conventional DFF-based PD. It shows that the NRZ data could be aligned and recovered by the only...
Tri-state inverter based DCO are emerging as an attractive circuit for the implementation of fully digital PLL. In this paper, we first introduce an analytical expression of the tuned period as a function of design and technology parameters. Then, we propose a sizing methodology for the CMOS implementation of a tri-state inverter based DCO. Finally, we applied this methodology to the design of such...
Digital intensive architectures allow for flexibly programmable frequency synthesis. Timing jitter and/or phase noise is an important quality criterion for synthesizers. This paper reviews fundamental limitations for jitter in digital frequency architectures, aiming at finding a basis to compare alternative architectures and optimize jitter performance. It motivates why the product of jitter variance...
Next generation optical and electrical communications such as chip-to-chip serial links or 100GbE require very-high-speed transceivers. At tens of Gb/s, both transmitters and receivers suffer from inadequate bandwidth and high power consumption. One major difficulty arises from the performance degradation of FIR-based FFEs as the FF's CK-Q delay becomes significant to one bit period. Using passive...
Burst-mode clock and data recovery circuits (BMCDR) are widely used in passive optical networks (PON) [1] and as a replacement for conventional CDRs in clock-forwarding links to reduce power [2]. In PON, a single CDR performs the task of clock and data recovery for several burst sequences, each originating from a different source. As a result, the BMCDR is required to lock to an incom ing data stream...
Recently, high-resolution TDCs have gained more and more popularity due to their increasing implementation in digital PLLs, ADCs, jitter measurement and time-of-flight measurement units. Similar to ADCs, existing architectures of TDCs can be divided into several categories: flash TDCs, pipeline TDCs, and SAR TDCs. The highest achievable time resolution of a TDC is mainly limited by the CMOS gate delay...
This paper presents a design and implementation of a low noise phase-locked loop (PLL) based on ring oscillator to provide timing clocks for the analog-to-digital converter (ADC). The ring oscillator consists of four current control delay cells with current-steering amplifier (CSA) circuit. These fully switching differential delay cells are employed to reduce the phase noise of the ring oscillator...
Today, a great concern for the integration of high-frequency systems are the problems associated with the synchronization difficulties. The VCO block of PLLs is the primary source of timing jitter and this work addresses issues significant to the design of VCOs with Single-Ended Control in PLLs. The main goal of this work is to develop Two high frequency CMOS PLLs in 0.13μm technology. The advantage...
In this paper, an ultra low power and low jitter 12bit CMOS digitally controlled oscillator (DCO) design is presented. Based on a ring oscillator implemented with low power Schmitt trigger based inverters. Simulation of the proposed DCO using 32nm CMOS Predictive Transistor Model (PTM) achieves controllable frequency range of 550MHz~830MHz with a wide linearity and high resolution. Monte Carlo simulation...
A Vernier Gate-Ring-Oscillator (GRO) Time to Digital Converter (TDC) is proposed and implemented in 90-nm CMOS process technology. It utilizes two GRO chains as the delay lines. The time resolution is determined by the difference between two delays, so not limited by the process. Moreover, the quantization noise can be first-order shaped by the gated behavior in the oscillators, which further improves...
A multi-port serial link with a wide-range CDR using digital Vernier phase shifting and dual mode control is presented. The proposed Vernier phase shifter generates fine-resolution phase steps and provides unlimited phase rotating. With the dual mode control, the proposed CDR extends the operating range from 250Mbps to 5Gbps. The proposed CDR provides 13.34ps phase steps at 5Gbps and achieves a BER...
This paper presents a digital scrambling technique to improve the linearity of flash time-to-digital converters (TDCs) with sub-gate-delay time resolution. Thanks to this approach, a flash TDC using N time arbiters behaves as a quasi-stochastic TDC with an equivalent number of samples equal to N2, at the negligible area cost of doubling the number of minimum load capacitors. The concept is proved...
In this paper, a small area spread-spectrum clock generator (SSCG) with high EMI reduction for SATA-3.0 is presented. Conventional methods use inductor-capacitance (LC) tank to fulfill the high frequency requirement for SATA-3.0. However, the monolithic inductors always occupy a large area, and required precisely characteristic for different fabrication processes. This research propose a SSCG using...
A 7-bit 360° phase rotator in 45nm CMOS interpolates between coarse phases by modulating the injection point of an oscillator. This architecture decouples phase resolution from device sizing. INL and DNL are improved by independently adapting the delay of each oscillator stage. A digital phase-locked loop using a time-to-digital converter based on a tracking ADC keeps the oscillator tuned to the injection...
Modern nano-scale CMOS technologies favor all-digital architectures for frequency synthesizers in wireless and other mixed-signal applications. This paper is a short introduction to the topic presenting contemporary approaches from a signal and systems perspective as well as directions for future research.
This paper presents a high resolution two-step gated-ring oscillator (TSGRO) time-to-digital converter (TDC) in an all digital phase-locked loop (ADPLL). TSGRO-TDC consists of a coarse step and a fine step gated-ring oscillator (GRO) TDC to achieve a high resolution. An edge aligner is used in the fine step GRO-TDC to enhance a first-order noise shaping property. A meta-stability free selection logic...
This paper presents a low noise fractional-N PLL that employs the reference multiplication technique. In order to reduce the noise from ΔΣ modulator (DSM) and charge-pump (CP), the proposed PLL increases the OSR of the DSM and reduces the gain of the CP to the output It employs dual phase detector (PD) architecture that can obtain the information of the phase error twice more frequently than a conventional...
A compact (0.01mm2) coarse-fine time-to-digital converter (TDC) in 40nm LP CMOS achieves 5.5ps resolution using parallel delay lines. A 6fJ/conversion step efficiency is achieved thanks to efficient residue calculation. A 0.8LSB single-shot precision and low DNL are reached thanks to simple calibration which is possible in fractional-N PLLs. Further, metastability avoidance and digital error correction...
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