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A two-point expression of effective drive current ($I_{\rm eff\_{}PG})$ for pass-gate (PG) transistors is proposed for the first time. We demonstrate that the proposed expression of $I_{\rm eff\_{}PG}$ estimates the PG latency with a reasonable accuracy (relative error <15%) under different technology nodes from 90 to 20 nm and a wide range of biasing conditions including gate overdrive voltage...
Near-threshold computing (NTC) is an effective technique for improving the energy efficiency of a CMOS microprocessor, but suffers from a significant performance loss and an increased sensitivity to voltage noise. MOS current-mode logic (MCML), a differential logic family, maintains a low voltage swing and a constant current, making it inherently fast and low-noise. These traits make MCML a natural...
An 8bit two-step time-to-digital converter (TDC) with a novel digital switched ring-oscillator based time amplifier (TA) is demonstrated in 65nm CMOS. The proposed TA achieves a predictable and programmable gain without requiring any calibration. The implemented 8bit two-step TDC with a 16x TA gain achieves a time resolution of 2.6ps at 80MS/s conversion rate while consuming 2mW. The measured DNL...
Power and area remain the main constraint in designing of VLSI circuits. Also, adder being one of the main components of processor design is highly researched digital module. In this paper high speed adders are designed using 130nm CMOS process and are being evaluated for their performance at lower technologies. The power dissipation, delay and area are compared for Carry select adder, ripple carry...
The power, speed, area and energy constraints are the major user concerns, when it comes to choosing the appropriate logic family for new applications. This paper introduces customizable logic families and presents a comparative analysis of such logic families, to enable the user to make a robust choice. Energy efficiency has been identified as one of the most required features for modern electronic...
The need for low power, area efficient and high speed comparator is pushing towards the use of clocked digital comparator which maximize speed and power efficiency. As CMOS technology scales down, various short channel effects arises which increases the leakage current due to low threshold voltage and waste some percentage of power as leakage power. This paper presents detail survey of low power techniques...
New low power dynamic MTCMOS full-adder cells have been proposed in this paper. Eight bit Domino and TSPC (True Single phase clock) adder circuits have been designed in 45 nm Multi-threshold CMOS Technology. The proposed MTCMOS dynamic adder circuits are faster as compared to static CMOS logic circuits. Due to the high-VT sleep transistor added, the leakage power of the circuits is also minimized...
Modern communication and signal processing is dependent on the high speed and low power consumption of the Analog-to-Digital converters (ADC) to a very large extent. Comparator is the basic building block of the ADCs which compares the two set of variables and change the input analog signal in digital. In this paper a new design of double tail comparator is proposed for high frequency of data conversion...
Multiple Dynamic Supply Voltage (MDSV) is an attractive way to reduce dynamic power in Integrated Circuits. This technique introduces Level Shifter (LS) in order to commute from one voltage domain to another. Nevertheless, some LS inserted during the physical synthesis can degrade performance and power consumption, especially in specific power modes. In this work, we present a novel approach to dynamically...
A novel high-speed and low-power negative level shifter suitable for low voltage applications is presented. To reduce the switching delay and leakage current, a novel bootstrapping technique is designed for the level shifter. Furthermore, a pull-down driver is proposed to have high driving capability under different operation modes. The circuit has been designed in 130 nm 1.5 V/5 V triple-well CMOS...
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