The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper, a novel signal toggling technique in Electrical Optical Frequency Mapping/ Phase Mapping (EOFM/EOPM) and Electrical Optical probing (EOF) are performed to successfully localized the fault location and identify the physical defect promptly. A function square wave is asserted into the pin of interest, i.e. leakage pin or the function power pin, for EOFM and EOF purposes. This technique...
Technology scaling has continuously improved the density, performance, energy efficiency, and cost of DRAM-based main memory systems. Starting from sub-20nm processes, however, the industry began to pay considerably higher costs to screen and manage notably increasing defective cells. The traditional technique, which replaces the rows/columns containing faulty cells with spare rows/columns, has been...
The cell-aware test (CAT) methodology was previously proposed to target cell-internal faults that cannot be easily detected by gate-level stuck-at fault (SAF) patterns generated by conventional ATPG. It was shown to reduce the defect level on CMOS-based designs, with the help of detailed defect injected transistor-level circuit simulation and defect-enhanced SAF ATPG. The detailed transistor-level...
The paper presents fault tolerant control algorithms of modified space vector pulse width modulation (SVPWM) for three-phase inverter supplies a PMSM in case of failure of one transistor leg. Fault tolerant inverter structure with four-switch is analyzed with taking into account the non-ideal DC link. Calculations of the desired voltage vector in the PMSM drive are presented. An optimal voltage vector...
The test complexity of high density DRAMs increases with technology evolution, due to a larger impact of process variation and weak defects. In particular, resistive open defects turn to be a major concern in DRAMs. Our analysis and simulation results show that an important phenomenon exists, charge accumulation, which is currently not considered in DRAM testing. Charge accumulation occurs in DRAM...
This paper present a new form to charge batteries with photovoltaic modules. The main element of the system is buck-boost converter based on three state commutating cell (3SCC). Here, the converter is used as voltage divider of dc bus battery bank of the micro-grid with photovoltaic modules.
We analyze the effects of faults on an energy-harvesting circuit (EHC) providing power to a wireless biomedical multisensor node. We show that such faults may prevent the EHC from producing the power supply voltage level required by the multisensor node. Then, we propose a low-cost (in terms of power consumption and area overhead) additional circuit monitoring the voltage level produced by the EHC...
We present, implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ?IDDQ testing of CMOS data converters. A 12-bit digital-to-analog converter (DAC) is designed as the circuit under test (CUT). The BICS uses frequency as the output for fault detection in CUT. A fault is detected if...
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
An on-line test methodology for MOSFET-C filters is presented, based on comparing the outputs from the different biquads in a filter to the output of a programmable biquad. The implementation of this biquad as well as that of a comparison circuit is discussed, and a design example is given.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.