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Two cases of transient latchup specific to power management analog integrated circuit design are described and analyzed experimentally. The representative case studies include the interaction of a power array and ESD clamp and the interaction of two high voltage ESD clamps.
A non-trivial nature of the power management circuit design is emphasized based on three case studies. The events of transient latchup and device failure under Charged Device Model (CDM) pulse due to an unexpected current path in power analog circuits are analyzed demonstrating the value of mixed-mode simulation approach.
This work investigates the ESD robustness of stacked drivers in bulk and SOI technologies. The impact of stacked driver sizing and pre-driver connection is examined in detail using VF-TLP and TLP measurement. It is shown that proper pre-driver configuration can double Vt2, thereby improving I/O's It2.
In this paper, the improved field-effect diode (FED) has been characterized and modeled in 45 nm silicon-on-insulator (SOI) technology. It has been experimentally shown to be suitable for pad-based local clamping under normal supply voltage (Vdd) range (below 1 V) in high-speed integrated circuits. ESD protection capabilities are investigated using very fast transmission line pulse (VF-TLP) tests...
The concept of Transient Safe Operating Area (TSOA) for electrostatic discharge (ESD) design is discussed in this paper. TSOA characterization is introduced to obtain ESD design targets and better synthesize protection-/core- devices actual transient over-voltage response for robust ESD performance in emerging high-voltage mixed-signal circuit applications. A first methodology based on the direct...
We have identified and explained a unique ESD breakdown mechanism of high voltage 80V LDMOS structures for very fast CDM transients. The device was protected against observed damage by placing a zener across the gate and source which prevents the observed voltage build up at the gate of the LDMOS.
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