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High-level synthesis (HLS) currently seems to be an interesting process to reduce the design time substantially. HLS tools actually map algorithms to architectures. While such tools were developed targeting ASIC technologies, HLS currently draws wide interest for FPGA designers. However with most of HLS techniques, traditional resource sharing models are very inaccurate for FPGAs: for example, multiplexers...
In this paper we address the time-constrained architectural synthesis of fixed-point DSP algorithms using FPGA devices. Optimized fixed-point implementations are obtained by means of considering: (i) a multiple word length approach; (ii) a complete datapath formed of word length-wise resources (i.e. functional units, multiplexers and registers); and, (iii) a novel resource usage metric that enables...
This paper describes the implementation of high-performance 32-bit embedded processor, Core-A. Core-A processor has unique instruction set architecture(ISA) in the form of reduced instruction set computer (RISC). Especially, Core-A processor has several unique features for code density and DSP applications. Since Core-A processor is described using Verilog HDL, it can be customized for a given application...
As the use of FPGAs increases, the importance of highly optimized processors for FPGAs will increase. In this paper we present the microarchitecture of a soft microprocessor core optimized for the Virtex-4 architecture. The core can operate at 357 MHz, which is significantly faster than Xilinxpsila Microblaze architecture on the same FPGA. At this frequency it is necessary to keep the logic complexity...
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