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Unlike traditional SoC (System-on-chip) chip, multiprocessor chip that contains multiple independent processors, each processor owns different applications, so we need to make a reasonable multiprocessor chip initialization program. This paper proposes a design for the multiprocessor system initialization. The main contribution is as follows: Firstly, one method for the implementation of multiprocessor...
Traditional evolutionary algorithms require a lot of memory and processing power on embedded logic projects. Representing populations of candidate solutions through vectors of probabilities rather than sets of bit strings saves memory and processing. The concise evolutionary algorithm (CEA) is a probability vector based evolutionary algorithm. The article presents an FPEA realization of the standard...
We present a design and implementation of a radix-4 complex division unit with prescaling of the operands. Specifically, we extend the treatment of the residual bound and errors due to the use of truncated redundant representation. The requirements for prescaling tables are simplified and a detailed specification of the table design is given. All principal components used in the design are described...
Based on the characteristics of FPGA, a boundary scan circuit with an extended instruction set in accordance with IEEE 1149.1 standard has been designed and presented in this paper. The circuit can implement the function of built-in self test (BIST) together with FPGA device-programming. In the design, the architecture of the circuit is simplified by deleting redundant instruction registers and sharing...
In this paper a methodology of symbolic RTL synthesis, for circuits implemented in FPGA devices, is presented. First, symbolic functions are separated from binary and arithmetic ones. Next, the multi-valued logic network is optimized using our methods of symbolic functional decomposition, designed for functions with multi-valued inputs and multi-valued outputs. Finally, the whole circuit is implemented...
Recent significant advancements in FPGAs have made it viable to explore multiprocessor solutions on a single FPGA chip. An efficient communication architecture that matches the needs of the target application is always critical to the overall performance of multiprocessors. Packet-switching network-on-chip (NoC) approaches are being offered to deal with scalability and complexity challenges coming...
Block memory or custom memory is one of the most important features in the Structured ASIC design. But block RAM is not suitable to form small memory array and also limited to the pre-defined location. On the other hand, the distributed memory is one of the most important features in FPGA to support small size memory application and available anywhere across the chip. But the distributed memory is...
This paper presents a novel method to perform on-the-fly attestation of hardware structures loaded to reconfigurable devices. Given that a loadable hardware structure to a reconfigurable device is described by a binary bitstream, the hash value of this bitstream can be calculated to validate the hardware structure. To optimize this attestation, the hash value computation is implemented in hardware...
Designing dependable systems is a systematic task where area, power and performance are competing constraints. In many applications, design restrictions do not permit the total hardening of a design, leaving some internal circuitry vulnerable to radiation effects. Hierarchical analysis is necessary to identify the relative importance and vulnerability of individual sub-circuits in a design so that...
As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. The resulting performance variation requires new design strategies to avoid pessimistic over-design. A quantified understanding of the contribution different circuit components make to performance variation is a necessary part of such strategies. This paper proposes...
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