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Most of the literature on image filtering using FPGAs focuses on the normal case when the window is completely within the image. The exception - when the window is partly off the edge of the image - is rarely considered. If not managed appropriately, handling these exceptions can take up more resources than the main operation. Efficient techniques are presented that manage the image borders by reusing...
Impulse noise removal is a very important preprocessing operation in many computer vision applications. This paper presents a noise removal approach based on a simple conditional technique. As evaluations show, the presented technique performs significantly better than standard median filter and achieves superior image quality. Experimental FPGA implementation of the proposed technique for window...
The H.264/AVC standard achieves much higher coding efficiency than previous video coding standards. Unfortunately mis comes with a cost in considerably increased complexity at the encoder mainly due to motion estimation. Therefore, various fast algorithms have been proposed for reducing computation but they do not consider how they can be effectively implemented by hardware. In this paper, we propose...
In this paper a new FPGA design concept of a bilateral filter for image processing is presented. With the aid of this design the bilateral filter can be realized as a highly parallelized pipeline structure with very good utilization of dedicated resources. The innovation of the design concept lies in sorting the input data into groups in a manner that kernel based processing is possible. Another feature...
This paper describes a FPGA-based verification methodology for the image signal processor (ISP) of system-on-chip (SoC) type CMOS image sensor. To make a verification environment, the complete ASIC prototyping system, the ARM7 TDMI CoreTile board and external interface boards - the sensor board, the USB board and the switch board - are used. As a verification method, 4-step verification strategy comprised...
Since Frame Rate Up-Conversion (FRC) is started to be used in recent consumer electronics products like High Definition TV, real-time and low cost implementation of FRC algorithms has become very important. Therefore, in this paper, we propose a low cost hardware architecture for realtime implementation of frame interpolation algorithms. The proposed hardware architecture is reconfigurable and it...
Motion estimation (ME) is the most computationally intensive and the most power consuming part of video compression and video enhancement systems. In this paper, we propose a novel power reduction technique for ME hardware. We quantified the impact of glitch reduction, clock gating and the proposed technique on the power consumption of two full search ME hardware implementations on a Xilinx Virtex...
The image foresting transform (IFT) is a general tool for the design of image processing operators based on dynamic programming. Silicon image forest transform (SIFT) is a fast 8-bit data architecture for IFT-based operators in FPGA. It can implement queue-based methods such as morphological reconstructions, watershed transforms, shape saliences, distance transforms, skeletonization, edge tracking,...
In order to realize fingerprint recognition system in real time environment, we describe in this paper signal controller to read fingerprint sensor generated in FPGA devices. Basically this signal is generated using state machine. The simulation result for behavioral simulation and signal generation read by logic analyzer are presented in this paper. Initialization and reading time for 76800 pixels...
A new processor architecture implementing the Discrete Time Cellular Neural Networks (DT-CNN) on FPGA is proposed. This architecture intends to process video images real time with 3times3 CNN templates and without the use of an external memory. The absence of the external memory decreases the cost and complexity of the system. The architecture is based on a single pipelined cell which is employed...
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