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In this paper, we propose a novel discontinuous spread spectrum clock generator with a low maximum time interval error (MTIE) and low electromagnetic interference (EMI). The proposed circuitry was fabricated with 0.35µm CMOS process and operated with 3.3V supply voltage at the average center frequency of 100MHz. The measured results showed the MTIE of 11.59ns with the EMI reduction of 14.57dBm.
In this paper, a novel Direct Digital Frequency Synthesizer (DDFS) based on using non-uniform segmentation in sine-weighted Digital-to-Analog Convertor (DAC) is proposed. To generating beyond Nyquist frequency signal, parallel DACs with Return-To-Zero (RTZ) technique are used. In conventional DDFSs for generating signal, a Phase to Sine Mapper (PSM) is used that often includes a look-up table memory...
An increased damping resistor (IDR) replaces high-order loop filter to simply reduce the total harmonic distortion (THD) of Class-D audio amplifier. Besides, cross offset cancellation (COC) technique minimizes the system offset voltage to avoid dc current flows to the speaker in the bridge tied load (BTL) structure. Furthermore, variable switching frequency characteristic in self-oscillating modulation...
The growth in communications coupled with the move towards multi-carrier, multi-band, multi-standard radio transmitters have helped drive high-speed digital-to-analog converter (DAC) technology for over a decade. The critical challenge for these DACs is realizing the highest possible signal purity at the DAC output. While DC linearity (from current source mismatch, for example) can be a factor, in...
The past several years have successfully brought all-digital techniques to the RF frequency synthesis, which is used for frequency translation between the baseband and RF frequencies in wireless transmitters and receivers. Reference [1] has described the recent journey of digitizing RF frequency synthesizers, such that now they are amenable to nanoscale CMOS technology with area, power and performance...
This paper proposes a reconfigurable, spectrally efficient 7-tap FIR pulse based UWB transmitter with the maximum pulse rate of 1.6Gpulses/s. By utilizing a Δ-Σ PLL and a DAC embedded FIR pulse generator, digitally configurable pulse generation is done with high spectral efficiency. For low power 7-tap FIR pulse generation, a 1/8-rate, 16-phase injection-locked oscillator (ILO) is designed instead...
We propose a new digital algorithm that can shape element mismatch and ISI errors simultaneously. This method fully shapes ISI and the mismatch errors outside audio band and eliminates the need for layout critical and non-automat ed analog design methods that often require multiple design iterations and are hard to migrate over processes. This is enabled by using digital processing circuits that are...
This paper presents a frequency-locked loop (FLL) based SSCG with frequency-to-voltage converter (FVC), that saves area and provides multiple δ with low bandwidth variation. A memoryless Newton Raphson modulation profile with multiple fm is also described.
The implementation of a fully integrated multi-standard low-jitter clock generator is presented. A ΣΔ fractional-N phase-locked loop (PLL) is chosen for 0.8 to 6.3 GHz wireline Serializer-Deserializer (SerDes) transmitting clock and spread spectrum clock generator (SSCG) for Serial AT Attachment (SATA I, II, III) characterized by a spread modulation of 5000 ppm. A multi-range voltage-controlled oscillator...
In this paper, an 1-bit second-order low-power ΔΣ modulator for pressure sensor applications is presented. The modulator utilizes correlated double-sampling (CDS) in order to reduce the flicker (1/f) noise. Due to the 1-bit output, the feedback DAC is inherently linear. The modulator is designed with 0.35-μm CMOS process. Measured signal-to-noise and distortion ratio (SNDR) is 86dB (14bits), while...
A spread spectrum clock generator (SSCG) based on an offset phase-locked loop (OPLL) for the Serial AT Attachment 3 (SATA-III) is presented in this paper. The SSCG can be applied to many systems due to its characteristic of spreading the energy of frequency harmonics and reducing the radiated power per unit bandwidth. In the proposed architecture, a low-frequency spread spectrum signal is synthesized...
This paper presents a 2.5-8Gb/s transceiver for PCI Express Gen3.0/2.0/1.0 applications. To overcome channel loss of high bit rate application, a linear equalizer (LEQ) and decision feedback equalizer (DFE) are used to eliminate ISI effect, compensate channel loss, and improve BER performance for 28-inch FR4 channel. The 3-tap feed-forward equalizer (FFE) is used to improve signal quality in transmitter...
A packet-switched 6×4 2D mesh network-on-chip (NoC) on a dedicated voltage and frequency island (VFI) provides 2 Tb/s of bisection bandwidth, and interconnects 48 Pentium™ class IA-32 cores and 4 DDR3 channels. The 1.28 Tb/s router with 16 B, 5.4 mm links achieves high network utilization through 8 virtual channels (VC), early-buffer write and read, route pre-computation and a 1-cycle wrapped wavefront...
A noise-shaped synchronous buck converter using a 3rd-order continuous-time (CT) active-passive sigma-delta modulator (SDM) is presented. Detailed system modeling and loop design methodology for the SDM based DC-DC are discussed. The proposed circuit has been designed with Chartered 0.35 μm CMOS process. The system operates with a clock of 8 MHz. Compared with the traditional PWM mode converter, simulation...
A 7-bit 360° phase rotator in 45nm CMOS interpolates between coarse phases by modulating the injection point of an oscillator. This architecture decouples phase resolution from device sizing. INL and DNL are improved by independently adapting the delay of each oscillator stage. A digital phase-locked loop using a time-to-digital converter based on a tracking ADC keeps the oscillator tuned to the injection...
A Δ-Σ fractional-N Phase-locked Loops (PLL)- based frequency synthesizer (FS) with a frequency range of 250 MHz to 4 GHz is presented. By employing the Δ-Σ fractional-N technique and utilizing the multi-phase clocks available in the ring-VCO of the PLL, the frequency synthesizer is capable of generating high-resolution and low-spur clocks with instant frequency switching. Moreover, the proposed FS...
We propose an all-digital offset PLL architecture in which the RF oscillator output is frequency translated through rotation of its quadrature phases before being fed back for the phase comparison with the frequency reference. This eliminates spurious tones caused by the finite resolution of the phase detection process when the synthesized frequency is very close to the integer-N multiple of the reference...
Digital implementation of analog function is becoming attractive in CMOS ICs, given the low supply voltage of ultra-scaled process. The conventional fractional-N frequency synthesizers suffer form the fractional spur due to the application of fractional divider. A new architecture of an all digital fractional-N phase-locked loop based frequency synthesizer is presented in this paper. The unique feature...
A fully integrated 77 GHz FMCW automotive radar system in 65 nm CMOS includes clock generation and chip-antenna assembly. Incorporating a full-rate fractional-N synthesizer and a high-performance RF front-end, the radar achieves a maximum detectable distance of 106 meters for a mid-size car while consuming 243 mW from a 1.2 V supply.
Implemented fractional-N frequency synthesizer architecture based upon Pulse Width Locked Loop technique eliminates the need for ???? modulator within the loop while preserving the frequency resolution and accuracy of such synthesizers. Eliminating the modulator allows the designer to optimize the synthesizer loop bandwidth without any constraint imposed by the modulator. The loop operates by locking...
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