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Timing analysis in embedded systems has focused mainly on the Worst-Case Execution Time (WCET) in the past. This was (and still is) important to make guarantees for the application of the system in safety critical environments. Today, two reasons call for a slightly changed perspective. Firstly, the complex and often unpredictable internal structure of modern system-on-chip architectures prohibits...
With FPGAs emerging as a promising accelerator for general-purpose computing, there is a strong demand to make them accessible to software developers. Recent advances in OpenCL compilers for FPGAs pave the way for synthesizing FPGA hardware from OpenCL kernel code. To enable broader adoption of this paradigm, significant challenges remain. This paper presents our efforts in developing dynamic profiling...
Classification is one of the core tasks in machine learning data mining. One of several models of classification are classification rules, which use a set of if-then rules to describe a classification model. In this paper we present a set of FPGA-based compute kernels for accelerating classification rule induction. The kernels can be combined to perform specific procedures in rule induction process,...
This paper discusses development of FPGA-based verification platform which consists of System' Verilog assertion (SVA) checker generator to synthesize SVA into Verilog code. We derive a lookup table that consists of SVA operators and their corresponding synthesizable RTL coding. Assertion checker produces single bit-1 which indicates an assertion fails while assertion collection modules must be simple...
Embedded system design involves meeting strict design goals such as performance, area and power consumption. In-order to meet these design goals embedded systems are implemented in programmable processors and application-specific hardware. Hardware/Software partitioning is thus, a critical step in the realization of embedded systems. The initial software description of the application is profiled...
In this work, we present a dedicated hardware implementation of exponential function computation unit using CORDIC (Coordinate Rotation Digital Computer) algorithm for extended range of input arguments. Hardware architecture design is done keeping in view its possible integration in the hardware implementation of the Radial Basis Function (RBF) based Support Vector Machine (SVM) classifier. The designed...
In order to enhance the characteristics of underwater ultrasonic imaging system with small volume, low power supply voltage and easy integration, the underwater ultrasonic phased transmitting system is designed. Using field programmable gate array (FPGA) to control the excitation signals time-delay of 16 channels to achieve phased transmitting, and capacitive micro-machined ultrasonic transducer arrays...
In this paper we propose a combination of capabilities of the FPGA based device for computing reduct. Presented architecture has been tested on a real-world data. Obtained results confirm the huge acceleration of the computation time using hardware supporting reduct computation in comparison to software implementation.
In this paper, a stochastic computation (SC) based hardware implementation for 4-point DCT in the emerging High Efficiency Video Coding (HEVC) standard was provided. HEVC employs integer DCT with larger transform coefficients than the preceding standards. Hence the multipliers and adders therein are also more hardware consuming. With SC theory applied to DCT hardware design, the circuit implementation...
Field-Programmable Gate Arrays (FPGAs) are able to provide hardware accelerators still maintaining the required programmability. However, the advantages of using FPGAs still depend on the expertise of developers and their knowledge of Hardware Description Languages (HDLs). Although High-level Synthesis (HLS) tools have been developed in order to minimize this problem, they commonly present solutions...
The development of new technologies and the increase of information handled by small devices has lead to a variety of new storage methods which heavily depend on compression algorithms. Previously, we demonstrated the advantages of using reconfigurable computing for the efficient implementation of a Huffman coding-based compression unit [1]. In this paper we built upon our last design and propose...
Embedded system designers can achieve energy and performance benefits by using dedicated hardware accelerators. However, implementing custom hardware accelerators for an application can be difficult and time intensive. LegUp is an open-source high-level synthesis framework that simplifies the hardware accelerator design process [8]. With LegUp, a designer can start from an embedded application running...
This paper analyzes the gray projection motion vector estimation algorithm to illustrate the application environment and the characteristics of this algorithm, Indicate the needed of resources when implemented in hardware circuitry. Point at the Characteristics of the algorithm we made the corresponding optimized to make it more suitable for the hardware calculation. We design the corresponding circuit...
K-means clustering has been widely used in processing large datasets in many fields of studies. Advancement in many data collection techniques has been generating enormous amount of data, leaving scientists with the challenging task of processing them. Using General Purpose Processors or GPPs to process large datasets may take a long time, therefore many acceleration methods have been proposed in...
Ethernet is synonymous with networking and its application is ubiquitous worldwide. Its popularity is in part due to its high bandwidth over long cable lengths and a driver-less architecture within an operating system environment. Communication over Ethernet has associated complexity, both in terms of the physical hardware the networking stack interface requirements. Hence, it is of great interest...
This paper presents two implementations of BLAKE hash family algorithm that has been selected as one of the SHA-3 competition finalist. The first implementation is a modification from the implementation of Beuchat et al. which significantly reduces the required ROM size up to 36% from the original requirement with small trade-off in additional logic circuit. The second implementation is an extension...
Matrix Multiplication is a basic operation that can be used in many applications of DSP. For raw matrix data cannot feed into Simulink Xilinx block directly, thus a new module needs to be designed to complete the matrix multiplication. The original method is straightforward, while consuming considerable hardware resources. In order to save the consumption, we propose a new method to design the matrix...
In this article, the hardware's structure, the interface circuit, and the application software of the ultrasonic distance measurement system based of SOPC (System On a Programmable Chip) were studied. FPGA (Field Programmable Gate Array) was used as the core chip to design the hardware that processed the signal of ultrasonic sensor. The driver signal for ultrasonic emitter and the counter module were...
Regular expression is an important approach which is widely used in string pattern matching. And in many pragmatic applications string pattern matching is the most compute intensive task which takes majority processing time, therefore, in order to improve system efficiency many works have been done around hardware implementation of regular expression matching. However, the traditional design approaches...
Proliferation of handheld devices and growing interests in pervasive computing has led to the need for more flexible communication solutions where a single device integrates various wired and wireless communication standards e.g. Asymmetric Digital Subscriber loop (ADSL), Very high speed Digital Subscriber Loop (VDSL), Digital Audio Broadcasting (DAB), Digital Video Broadcasting (DVB-T/H) and 802...
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