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This work presents an efficient implementation of a softcore multiplier, i.e., a multiplier architecture which can be efficiently mapped to the slice resources of modern Xilinx FPGAs. Instead of dividing the multiplication into the generation of partial products and the summation using a compressor tree, as done in modern multipliers, an array-like architecture is proposed. Each row of the array generates...
A generalized pipeline array appeared in IEEE Trans. several years ago. The array can do various arithmetic operations in the pipeline manner. In this paper, the simulation of the array by using Cadence and Xilinx is discussed. The design implementation using Cadence, Xilinx and FPGA is further included in this paper. The purpose of this research is to develop a unified procedure for the design of...
The paper is about the implementation of PCT multiplier whose design is based on multiplexer using Field Programmable Gate Array (FPGA). Multiplier is such an important element from the point of power consumption and area occupied in the system. Multiplication using truncated scheme provides an efficient method for reducing the power and area as compared to that of full width multipliers. There are...
In this paper, a novel multiplier architecture based on ROM approach using Vedic Mathematics is proposed. This multiplier's architecture is similar to that of a Constant Co-efficient Multiplier (KCM). However, for KCM one input is to be fixed, while the proposed multiplier can multiply two variables. The proposed multiplier is implemented on a Cyclone III FPGA, compared with Array Multiplier and Urdhava...
FPGA is used in various current applications like telecommunications, airline traffic control and railway traffic control. So it is essential to evaluate the reliability of the FPGA. It is generally done using the specialized phenomena called as fault injection. The fault injection is done using the instrumented circuit that is being proposed on the paper. Where in the reliability of the combinational...
Matrix Multiplication is a basic operation that can be used in many applications of DSP. For raw matrix data cannot feed into Simulink Xilinx block directly, thus a new module needs to be designed to complete the matrix multiplication. The original method is straightforward, while consuming considerable hardware resources. In order to save the consumption, we propose a new method to design the matrix...
In this paper we describe an efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA. VHDL is used to implement a technology-independent pipelined design. The multiplier implementation handles the overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a Multiply and Accumulate (MAC)...
Interpolation is a basic concept in all fields of science and technology. Calculating the neighboring weights of an un interpolated data is found. This can be done effectively by partial volume interpolation, because it produces smooth changes with small changes in transformation and improves subvoxel accuracy. Partial volume interpolator consists of multipliers as its main component. In this work,...
Demand for use of FPGAs in space is increasing to support hardware repair and hardware update functions in addition to software repair and update functions in spacecraft, satellites, space stations, and other applications. Under a space radiation environment, embedded devices must allow for incidence of high-energy charged particles. Such incidence can cause single or multi-event latch-up (S/MEL)-associated...
This paper presents a novel parallel System-on-Chip (SoC) memory architecture for a stereo vision system as required in 3D TV applications. It allows for a parallel access to all pixels located in a chosen window of the image. Using this architecture a complete window refresh on each clock cycle is possible, which can be used to increase the depth range of a stereo vision algorithm. This architecture...
This paper presents the implementation of a Maximum Power Point Tracker (MPPT) for photovoltaic (PV) applications by using multilevel boost converter and FPGA Board. The control algorithm for extracting maximum power from the cell is proposed by means of the VHDL code and implemented using Xilinx XC3S400 FPGA Board. In this work, a practical implementation of the real-time Estimate Perturb and Absorb...
To date, optically reconfigurable gate arrays (ORGAs) have been developed to realize large virtual gates and to increase gate array performance by combining a holographic memory with a programmable gate array. Among such studies, a 16-context ORGA architecture with nanosecond-order reconfiguration capability has already been demonstrated. However, its reconfiguration contexts are too few to execute...
A cellular array architecture suitable for implementing fault-tolerant logic on nanoscale fabrics is described in this paper. A simple logic cell that is optimized for arithmetic logic functions allows efficient implementation of signal processing functions. Compared to the typical look-up table (LUT) approach used in FPGAs, the proposed logic block has decreased flexibility in terms of reconfigurability...
The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic architectures. The novel FPGA structure is based on the combination of CMOL (Cmos + MOLecular scale devices) FPGA circuits and recent improvements and generalization of the CMOL concept to allow multilayer crossbar integration, compatibility...
This paper describes EDA technology, its basic characteristics and development process to a certain description. The status of programmable logic devices and the structural characteristics are introduced, focusing on the current popular FPGA technology. The main purpose of this paper is based on the current design of the popular FPGA devices, an autonomous experimental platform. Its low cost, easy...
Advanced encryption standard (AES) maintains safety and is used for providing security since publishing date. At the present day, crypto devices are produced in order to be smaller and faster. So, AES chips should not only use very small area, but also have enough throughput. In this paper, we present an 8-bit implementation of the AES algorithm which encrypts plaintext with 14.3 Mbps throughput and...
In Embedded Systems, the calculation of RSA cryptographic operations is sometimes hard to achieve if time constraints must be observed. In the following, we present an approach to increase processing power regarding cryptographic operations using FPGA (Field Programmable Gate Array) technology. The FPGA, which is present in many designs anyway, computes parts of the operations, allowing the embedded...
Many n-D signal processing applications require realization in real time. We propose the realization of a 3-D spatio-temporal wave digital filter (WDF) in an FPGA. Optimization of the implemented hardware architecture includes evaluation of two different kinds of overflow handling, namely by saturation and a ldquomodulo 2rdquo type operation. The FPGA board is processing DVI signals that can be provided...
It has become clear that on-chip storage is critical for most applications on FPGAs. In order to utilize on-chip storage efficiently, scholars have done some researches on implementing user memory models with embedded single-port and dual-port arrays. Their work is based on the assumption that user memory models are either single-port or dual-port. However, in some applications, user memory models...
With the evolution of programmable structures, that become more heterogeneous, the process of mapping a design into these structures becomes more and more complex. Modern FPGA chips are equipped with embedded memory blocks that can be used to increase the implementation quality of the design. The paper presents a logic synthesis method based on balanced decomposition that uses the concept of r-admissibility...
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