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In this paper, design of a novel Network on Chip (NoC) structure and its integration with Reliable Reconfigurable Real Time Operating System (R3TOS) are presented. NoC has been recently identified as a scalable communication paradigm to avoid the communication bottleneck in bus based communications. Dynamically Reconfigurable Field Programmable Gate Array (FPGA)s are particularly suited for applications...
In this paper, design of a novel reliable Application Specific Network on Chip (ASNoC) with reconfigurability and its integration with Reliable Reconfigurable Real Time Operating System (R3TOS) is presented. Network on Chip (NoC) is a well known scalable communication paradigm to avoid the communication bottleneck in bus based communications. Reconfigurable Field Programmable Gate Arrays (FPGAs) are...
In this paper, novel hardware architecture for performing point, line and edge detection using DAA is proposed. Such manipulations are vital in digital image processing applications and in the literature most of the implementations are on software platform only, especially in Matlab. Distributed Arithmetic Architecture (DAA) is widely used to implement inner product computations with fixed inputs...
In this paper, a squarer based on Vedic mathematics is proposed. Vedic mathematics is one of the ancient Indian mathematics which contains sixteen sutras. These sutras can be used to solve problems in any branch of Mathematics in a faster way. The proposed squarer is based on sutra called Ekadhikena Purvena. It means that “one more than the previous”. This sutra is used for finding the square of decimal...
In this paper, a novel multiplier architecture based on ROM approach using Vedic Mathematics is proposed. This multiplier's architecture is similar to that of a Constant Co-efficient Multiplier (KCM). However, for KCM one input is to be fixed, while the proposed multiplier can multiply two variables. The proposed multiplier is implemented on a Cyclone III FPGA, compared with Array Multiplier and Urdhava...
This paper presents a hardware implementation of multilayer feed forward neural networks (FFNN) using Field Programmable gate arrays (FPGAs). In spite of huge improvements in FPGA densities, the number of multipliers in a NN limits the size of the network that can be implemented using a single FPGA and the NN applications are not made commercially viable. The proposed implementation is aimed at reducing...
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