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A novel Built-in Self-Test (BIST) approach to test the configurable Input/Output buffers in Xilinx Virtex series SOCs using Hard Macro has been proposed in this paper. The proposed approach can completely detects single and multiple stuck-at gate-level faults as well as associated routing resources in I/O buffers. The proposed BIST architecture has been implemented and verified on Xilinx Virtex series...
A built-in self-test (BIST) approach is presented for the configurable logic blocks (CLBs) in Xilinx Virtex-5 field programmable gate arrays (FPGAs). A total of 17 configurations were developed to completely test the full functionality of the CLBs, including distributed RAM modes of operation. These configurations cumulatively detect 100% of stuck-at faults in every CLB. There is no area overhead...
This paper presents a built-in self-test (BIST) approach for testing configurable logic and memory resources in Xilinx Virtex FPGAs using hard-macro. The resources under test include the configurable logic blocks (CLBs) and block random access memories (BRAMs) in all of their modes of operation. The proposed approach completely detects and diagnoses single and multiple stuck-at gate-level faults of...
With the increased use of FPGA in widespread applications, its?? size and speed has been rapidly increased, so more and more problems associated with performance defects are emerging. Performance defects such as delay defects will not lead to a functional fault, but will limit the frequency of the system. Only Stuck-at testing has not been sufficient to guarantee the reliability and quality, so testing...
Built-in self test (BIST) and built-in self repair (BISR) techniques have been developed for memory blocks in recent years. Such techniques are suited to enhance production yield, but also to facilitate long-term dependable circuits though self repair in the field of application. BISR for logic circuits has shown to be much more complex, for which only a few approaches have been published so far....
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