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Smart City is becoming a commonly-used term to describe the concept of utilizing information and communication technologies (ICT) to enhance urban services and improve the quality of life for citizens. All communications should be fast and properly protected against unauthorized eavesdropping, interception, and modification. Therefore high speed and strong cryptography is required. Advanced Encryption...
Authenticated ciphers are cryptographic transformations which combine the functionality of confidentiality, integrity, and authentication. This research uses register transfer-level (RTL) design to describe selected authenticated ciphers using a hardware description language (HDL), verifies their proper operation through functional simulation, and implements them on target FPGAs -- the Xilinx Virtex-6...
Reconfigurability is a unique feature of modern FPGA devices to load hardware circuits just on demand. This also implies that a completely different set of circuits might operate at the exact same location of the FPGA at different time slots, making it difficult for an external observer or attacker to predict what will happen at what time. In this work we present and evaluate a novel hardware implementation...
Advanced Encryption Standard (AES) is the most widely used public cipher algorithm for crypto related applications in embedded systems. This paper presents an area efficient 16-bit AES architecture for key expansion, encryption and decryption. In the proposed design, a modular approach is adopted and it is capable of performing all transformations for 128, 192 and 256-bit cipher key lengths. The resources...
Embedded processors are an integral part of many communications devices such as mobile phones, secure access to private networks, electronic commerce and smart cards. However, such devices often provide critical functions that could be sabotaged by malicious entities. The supply of security for data exchange on basis of embedded systems is a very important objection to accomplish. This paper focuses...
In this paper, we propose a parameterized crypto co-processor based on Advanced Encryption Standard (AES). This parameterized AES module is combined with a 32-bit general purpose 5-stage pipelined MIPS processor. The AES module used in this paper is fully pipelined. The processor fetches an instruction from the instruction memory and sends it to the decode stage. If the instruction is the crypto instruction...
The reconfigurable processors like FPGA are extensively used for cryptographic applications which have reduced the time to market of the hardware logic. This paper describes the high performance pipelined hardware implementation of RC5 algorithm in Xilinx Vertex II Pro FPGA with a 12-stage pipeline scheme that has achieved an encryption rate of 6.9 Gbps. The proposed design operates on 12 input data...
Article presents modification for the cryptographic hardware accelerators. Modification, which allows for add new functionality to cryptography systems. Functionality allows for the dynamic changes in the number of rounds with maintaining uniformity in the processes of encryption and decryption. The proposed modification was discussed on DES algorithm example.
An FPGA implementation of the 128-bit SEED block cipher is presented in this paper. The proposed architecture achieves high-speed with little hardware resources using feedback logic and inner pipeline with negative edge-triggered registers. In this way, the delay of the critical path is reduced, without increasing the latency of cipher execution. The proposed implementation reaches a data throughput...
Self-healing systems can restore their original functionality by use of run-time self-reconfiguration, a feature supplied by state of the art FPGA devices. Commonly, integrity checks are performed by reading back the device configuration and validating its hash value. Systems which are prone to tampering and piracy of intellectual property may disable configuration readback, which renders this method...
This paper presents an FPGA implementation of the Advanced Encryption Standard (AES), using a Minimal Instruction Set Computer (MISC) architecture. The MISC's architecture is simple and reconfigurable to execute fundamental instructions with just simple hardware logic components. Due to the MISC's simplicity, it can be further extended to data encryption systems for certain applications like wireless...
This paper discusses design and analysis of an FPGA-based system containing two isolated, Altera Nios II softcore processors that share data through two custom crypto-engines. FPGA-based Single-Chip Cryptographic (SCC) techniques were employed to ensure full red/black separation. Each crypto-engine is a hardware implementation of the Advanced Encryption Standard (AES), operating in Galois/Counter...
Wireless sensor network has been widely used and its real-time data processing capability is very limited. This paper puts forward a new solution, which is the novel wireless sensor network node design with hyperchaos encryption based on FPGA. With the wide application on wireless sensor network based on ZigBee protocol, we encrypt the transported data in the network using hyperchaos by FPGA, which...
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