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Hardware Trojans have become a growing concern in the design of secure integrated circuits. In this work, we present a set of novel hardware Trojans aimed at evading detection methods, designed as part of the CSAW Embedded System Challenge 2010. We introduced and implemented unique Trojans based on side-channel analysis that leak the secret key in the reference encryption algorithm. These side-channel-based...
In this paper, an efficient method for high speed hardware implementation of AES algorithm is presented. So far, many implementations of AES have been proposed, for various goals that effect the SubByte transformation in various ways. These methods of implementation are based on combinational logic and are done in polynomial bases. In the proposed architecture, it is done by using composite field...
In this paper, compact architectures for AES Mix Column and its inverse is presented to reduce the area cost in resulting AES implementation. In the hardware implementation of AES with direct mapping substitute byte optimization, MixColumn/Inverse MixColumn transformation demands the utilization of logic resources and then effects the critical path delay and resulting throughput. The proposed MixColumn/Inverse...
Network security applications such as to detect malware, security breaches, and covert channels require packet inspection and processing. Performing these functions at very high network line rates and low power is critical to safe guarding enterprise networks from various cyber-security threats. Solutions based on FPGA and single or multi-core CPUs has several limitations with regards to power and...
The article presents a pipeline implementation of the block cipher CLEFIA. The article examines three known methods of implementing a single encryption round and proposes a new fourth method. The article proposes the implementation of a key scheduler, which is highly compatible with pipeline encryption. The article contains a detailed analysis of the data processing path for the 128-bit key version...
In this paper a hardware-in-loop simulator is presented to demonstrate the satellite sensor network concept developed at the Surrey Space Centre under the ESPACENET project. The simulator includes software that emulates satellite orbit dynamics in Low Earth Orbit and picosatellite sensor nodes. The picosatellite currently under development is based on the CubeSat platform. The main payload will be...
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