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Due to technology scaling, which means smaller transistor, lower voltage and more aggressive clock frequency, VLSI devices are becoming more susceptible against soft errors. Especially for those devices deployed in safety- and mission-critical applications, dependability and reliability are becoming increasingly important constraints during the development of system on/around them. Other phenomena...
In this paper, we developed a comprehensive single-event upset (SEU) analysis tool. To achieve this goal we start by defining the SEU mitigation strategy as a combination of chip level methods and system level methods. Given a particular SEU chip level and/or system level mitigation choice, we propose first categorizing the SEU Failure In Time (FIT) into different time window bins based on SEU recovery...
A high data reliability for high-speed transmission of LDPC-OFDM wireless communication system architecture is proposed with the implementation plan by the field programmable gate array(FPGA). Using the orthogonal properties of OFDM sub-channels can be transmitted over a combination of coding and decoding LDPC codes in the high performance, will achieve good results in communication system. The LDPC-OFDM...
MIL-STD-1553B is an avionics bus which is adopted widely, but the 1553B ASIC is difficult to be reprogrammed and modified. This paper proposes using the portability, highly integration and in-system programmable (ISP) performance characteristics of FPGA, and designing 1553B bus interface chip based on FPGA. The following designs of 1553B bus interface chip were completed in VHDL language on QuartusII,...
FPGA has been used in many robotics projects for real-time image processing. It provides reliable systems with low execution time and simplified timing analysis. Many of these systems take a lot of time in development and testing phases. In some cases, it is not possible to test the system in real environments very often, due to accessibility, availability or cost problems. This paper is the result...
Safety Logic (SL) System is a safety critical system provided to protect the Prototype Fast Breeder Reactor (PFBR) against various neutronic & thermal incidents. SL system receives trip parameters from various systems such as neutron flux monitoring, failed fuel detection, sodium flow monitoring, reactor inlet temperature monitoring etc and performs logical operations to drive Electro Magnet (EM)...
Advent of VLSI technology has paved the way for Programmable Logic Devices (PLD), which are widely used as the basic building blocks in high integrity electronic systems. PLDs are considered for their robust features such as high gate density, performance, speed etc. For PFBR Instrumentation and Control systems, PLDs are extensively used to implement digital designs such as VME bus interface logic,...
This paper proposes Flex Core, a hybrid processor architecture where an on-chip reconfigurable fabric (FPGA) is tightly coupled with the main processing core. Flex Core provides an efficient platform that can support a broad range of run-time monitoring and bookkeeping techniques. Unlike using custom hardware, which is more efficient but often extremely difficult and expensive to incorporate into...
A yield ramp methodology for Field-Programmable Gate Array (FPGA) in advanced technologies has been presented. By optimizing design based defect inspection setups, we can use defect-to-bit overlay mapping method more effectively and more reliably in product failure debug. This is complimentary to the manufacturing fab's test vehicles, electrical tests and physical failure analysis for faster wafer...
To achieve the strict requirements for rapidness of data acquisition and the precision of data transmission during the on-line monitoring system of the condition of circuit breaker, a design approach for real-time data acquisition and remote transmission system base on field programmable gate arrays (FPGA) and ARM technology is presented. The approach adopts an overall structure of FPGA + ARM + ICC...
In this paper, a leading indicators based approach has been developed for prognostics and health monitoring of electronic systems. The approach focuses on the prefailure space and methodologies for quantification of damage progression and residual life in electronic equipment subjected to shock and vibration loads using the dynamic response of the electronic equipment. Traditional health monitoring...
This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.
An on-line monitoring system for the insulation condition of capacitive-type equipment is described. The system adopts a distributed and layered multi-CPU structure, which is composed of the on-site measuring and processing unit, and data management and diagnosis system in the control room of substation. The on-site measuring and processing unit is based on DSP+FPGA hardware platform. Thus, the hardware...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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