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Multiport CMOS cell with the soft-error immunity based on DICE which is divided into two spaced groups of transistors each of them consisting of four transistors. The larger the distance between these two CMOS transistor groups, a multiport SRAM is more hardened to single event upsets. The result of a single nuclear particle strike only on the one transistor group of a DICE trigger is a single-event...
In this paper, we deal with a preventive maintenance (PM) scheduling and spare parts problems for a rolling stock system. We determine the optimal PM interval and the optimal number of spare parts for components in the rolling stock system to minimize the system life cycle cost during satisfying the system target availability. The system availability and system life cycle cost are estimated by simulation...
Reliability, availability, and maintainability (RAM) are three very important and necessary disciplines that must be applied within the system engineering process to ensure program success. The best way to generate success for a system is to overlay reliability engineering principles on the system engineering lifecycle, applying a phase-by-phase approach to drive RAM into the design. Beginning very...
Cell array architecture for floating body RAM of 35 nm bit line half pitch is described. The quasi-non-destructive-read-out feature of floating body cell contributes to eliminating inter-bit line coupling noise in open bit line architecture without degrading the cycle time of the RAM.
Life Cycle Cost (LCC) is used as a cost effective decision support for maintenance of railway track infrastructure. However, a fair degree of uncertainty associated with the estimation of LCC is due to the statistical characteristics of Reliability, Availability and Maintainability (RAM) parameters. This paper illustrates a methodology for estimation of uncertainty linked with LCC, by a combination...
This paper describes a new method of random access memory faults description using VHDL language. The fault injection technique, which uses behavioral synthesis VHDL descriptions, is proposed. The injection can be easily automated for memory test algorithms verification using only VHDL language and standard simulation software. No other applications and simulation tools are needed.
The ever changing demands on computational resources has information systems managers looking for solutions that are more flexible. Using a ldquobigger boxrdquo that has more and faster processors and permanent storage or more random access memory (RAM) is not a viable solution as the system usage patterns vary. In order for a system to handle the peak load adequately, it will go underutilized much...
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