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In this paper, implementation of an energy-efficient, low power, noise immune 4×4 Vedic Multiplier is proposed. The adder circuit used as building block in the multiplier unit is designed using semi-domino logic. The proposed multiplier unit has its benefits in terms of power consumption, delay, Energy-Delay-Product and UNG. This circuit exhibits a lower EDP of 2.88 Tena Micro to 27.97 Tena Micro,...
Significant challenges imposed on the design and optimization of clock-dependent systems have re-sparked interest in alternative circuit design approaches. Null Convention Logic, a quasi-delay-insensitive asynchronous design paradigm has gained significant support recently due to its intuitive circuit design and optimization approaches as well as its readiness for design automation. Just as for synchronous...
With emerging high performance digital circuits, the need for data converters with high accuracy, high speed and low power for various kinds of applications has increased greatly. Extensive researches are being conducted in order to decrease the size of data converters to obtain low power and high speed characteristics. Digital to Analog Converters (DACs) convert digital signals to analog signals...
Adders are basic building blocks of any processor or data path application. For the design of high performance processing units high speed adders with low power consumption is a requirement. Carry Select Adder (CSA) is known to be one of the fastest adders used in many data processing applications. In this paper, we present a new CSA architecture using Manchester carry chain(MCC) in multioutput domino...
In this paper, a novel modified 4T Content addressable memory (CAM) cell based Master-Slave Match Line (MSML) design for memory architectures is proposed. In memory architectures, match lines (MLs) and search lines (SLs) are main source of power consumption. The Proposed Modified 4T CAM cell based MSML design which reduces delay by 74%–95% with increases total power consumption and area compared with...
The main building blocks used in digital signal processing and multimedia applications are the adders and multipliers. Better the performance of adder structure better will be the performance of multipliers in total aspect. Reducing power dissipation, delay and area at the circuit level is considered as one of the major factors in developing low power systems. In this we present different topologies...
In this paper, a novel low power 4T content addressable memory (CAM) cell based Master-Slave Match Line (MSML) design for memory architectures is proposed. In memory architectures, match lines (MLs) and search lines (SLs) are main sources of power consumption. The proposed 4T CAM cell based MSML design reduces the area by 25%, delay by 11%–30% and total power consumption by 62% compared with 6T CAM...
There is no doubt that the CMOS technology scaling affects significantly the performance of the one-transistor one capacitor dynamic-random access memories (1T-1C DRAMs). In this paper, the effect of CMOS technology scaling and the change of the fabrication techniques of the access transistor and the cell-storage capacitor on the performance of DRAMs are investigated and discussed qualitatively. The...
The poor noise margin (NM) and power dissipation has becomes a severe issue in scaled semiconductor device technology. The memory array is major contributors in total power consumption because the most of the time array are utilized for on-chip caches in advanced microprocessors. In this work, the novel eight transistors (8T) cell characterized to improve the read mode noise margin (RMNM), write mode...
In this paper, we present a low-power, low-noise and wide dynamic range biosensor for neurotransmitter detection that exhibits high sensitivity and linearity. The design uses a fully differential difference amplifier (FDDA) to decrease the number of amplifiers in the control part, with reduced overall power consumption as a result. Moreover, this amplifier provides an output voltage swing that is...
In the recent trends the need for low power and less on-chip area is on high note for the portable devices. To cope up with the arising need, a new Magnitude Comparator is proposed with low power and less on-chip area for different range of lower supply voltages using Modified GDI technique implemented in 45nm process technology using CADENCE VIRTUSO. There is 95% and 67% reduction in power at lower...
A new sensing architecture aiming at negative threshold voltage detection for 3D NAND Flash memory cells is proposed. This sensing architecture does not need triple well devices and negative voltage supplies. In this architecture, we apply 2 V to source line (SL) rather than 0V which is always used in conventional method. We prove that this architecture is feasible by Technology Computer Aided Design...
A Content Addressable Memory is a memory unit which compares input search data against a table of stored data and returns the address of the matching data which is retrieved within single clock cycle. The CAM consumes more power due to parallel search operation and the designing issues of the CAM are to reduce the power consumption, area and to improve performance. The proposed architecture is based...
In this paper, an efficient method of partial product reduction is analysed. there are a number of techniques for partial product reduction it can be use of Wallace and Dadda schemes or can be use of compressor. Here we have studied a number of techniques for partial product reduction and came to a conclusion that compressors are better among them and we have inserted a concept of sleep transistor...
Standard cell design and memory design need to be optimized for sub-threshold operation. It is interesting to revisit digital block architectures when implemented using these sub-threshold basic bricks. Out of many possible architectures for the same logic function (i.e. Multiplier), it turns out that there are optimal sub-threshold architectures.
Speed and the overall performance of any digital signal processor are largely determined by the efficiency of the multiplier units present within. The use of Vedic mathematics has resulted in significant improvement in the performance of multiplier architectures used for high speed computing. This paper proposes 4-bit and 8-bit multiplier architectures based on Urdhva Tiryakbhyam sutra. These low...
The variety of applications for field programmable gate arrays (FPGAs) is continuously growing, thus it is important to address power consumption issues during the operation. As technological node shrinks, leakage power becomes increasingly critical in overall power consumption of FPGA. The technique of configuration pre-fetching (loads configurations as soon as possible) adopted to achieve high performance...
As the dark silicon era is about to embrace, it is not anymore possible to attain commensurate performance benefits by increasing the number of transistors due to thermal design power. Dark Silicon issue stresses that a fraction of silicon chip being able to switch in full frequency is dropping and designers will soon face the growing underutilization inherent in future technologies. On the other...
Multiple Dynamic Supply Voltage (MDSV) is a technique that focuses on reducing the dynamic power. This technique is an evolution of the Multiple Supply Voltage (MSV). MSV and MDSV introduce some difference on traditional physical synthesis due to the different voltage operations of each region in the design. To convert the voltage among regions supplied by different voltages, these techniques insert...
As we move to integration levels of 1,000-core processor chips, it is clear that energy and power consumption are the most formidable obstacles. To construct such a chip, we need to rethink the whole compute stack from the ground up for energy efficiency — and attain Extreme-Scale Computing. First of all, we want to operate at low voltage, since this is the point of maximum energy efficiency. Unfortunately,...
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