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In this paper, a novel new package solution for CMOS image sensor (CIS) based on molding compound interconnect substrate (MIS) is proposed. First, a 13 million pixel CIS packaged by quad flat no lead (QFN) is chosen as a reference. Considering the design parameters, a new package structure based on MIS is designed. Second, Two kinds of three-dimensional finite element models of CIS package are respectively...
Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 ??m CMOS technology. We present results for crystalline gadolinium oxides on silicon in the cubic bixbyite structure grown by solid source molecular beam epitaxy. On Si(100), crystalline Gd2O3 grows usually as (110)-oriented domains, with two orthogonal in-plane orientations...
CMOS technologies for mobile systems require integrated high voltage devices to address analog baseband and RF power applications. Technology and device architecture evolution, from 0.5 mum BCD-like to advanced 45 nm CMOS, on bulk and thin SOI substrates, are reviewed in this paper. Main challenges encountered when integrating these devices in advanced CMOS are explained. The influence of the gate...
A self-isolating, lateral IGBT device with high voltage blocking capability (>700 V), high on-state current density (150 A/cm2 at Vds=4 V) and very fast turn-off (< 50 ns), realized in membrane on bulk Si technology is reported here. The device has been manufactured using a standard 5 V, 0.35 mum bulk CMOS process on 8" wafers with the addition of two masks: i) n-drift for the HV blocking...
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO2. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
Simple ring-oscillator circuit has been used to estimate the degradation in circuit performance due to negative bias temperature instability (NBTI) effect but it fails to isolate the degradation from the NBTI for PMOS and the positive bias temperature instability (PBTI) for NMOS in high-K dielectric/metal gate CMOS technology. In this paper, we propose new circuit structures which monitor the NBTI...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
Design and characterization of a new generation of single-photon avalanche diodes (SPAD) array, manufactured by ST-Microelectronics in Catania, Italy, are presented. Device performances, investigated in several experimental conditions and here reported, demonstrate their suitability in many applications. SPADs are thin p-n junctions operating above the breakdown condition in Geiger mode at low voltage...
As the conventional scaling of CMOS technology is reaching its physical limitations, new materials and processes hold promise of giving CMOS a new lease on life. In order to turn an opportunity into a reality, the semiconductor industry is confronted with a daunting task of managing and co-integrating an unprecedented confluence of innovative approaches: high-k dielectric materials (HfO2, HfSiON)...
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