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Power supply noise and ground bounce can significantly impact the circuit's performance. Existing delay testing techniques do not capture the impact of combined and uncorrelated power supply noise and ground bounce for critical path delay analysis. They capture the worst case power supply noise in order to obtain the worst case path delay. We show that such assumption is not necessarily sufficient...
In this paper, the Power Electronic Load (PEL) is designed for power source tests. It consists of two power stages: input imitation converter and output grid-connection converter. The input imitation converter is used to test the tested AC power sources performance by imitating various linear loads and nonlinear load; the Grid-Connected Converter (GCC) keep the energy feed back to the grid and hold...
Decoupling capacitors (decaps) are typically used to reduce the noise in the power supply network. Because the delay of gates and interconnects is affected by the supply voltage level, decaps can be used to improve the circuit performance as well. In this paper, we present the analytical delay model under IR drop, Ldi/dt noise, and decaps to study how decaps affect both the gate and interconnect delay...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
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