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CλaSH is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. Polymorphism and higher-order functions provide a level of abstraction and generality that allow a circuit designer to describe circuits in a more natural way than possible with the language elements found in the traditional hardware description languages...
A verification environment which is based on a constrained random layered test bench using SystemVerilog OOP is implemented in this paper to verify the functionality of DUT designed with synthesizable constructors of SystemVerilog. Although the uses of multiple inheritance in OOP appear to be less common than those of single inheritance, multiple inheritance is useful for creating class types that...
Current practices for the design and deployment of hardware redundancy techniques in embedded systems remain in practice specific (defined on a case-per-case basis) and mostly manual. This paper addresses the challenging problems of engineering fault tolerance mechanisms in a generic way and providing suitable tools for coping with their deployment. This approach relies on metaprogramming to specify...
This paper presents an automated framework for obtaining high-performance FPGA implementations of industrial automation and control algorithms coded as PLC programs. The proposed method is mainly targeting demanding applications, requiring lots of numerical computations. Based on previous experience, the proposed framework exploits electronic system level modeling methodologies and tools for high-level...
This demonstration presents an integrated environment that translates a CAL-based dataflow specification [1] into a heterogeneous implementation, composed by HDL and C codes. The demonstration focuses on the capability of the co-design environment to automatically build an executable heterogeneous system implementation running on a platform composed of a processor and a FPGA from the annotation of...
The hArtes -holistic approach to reconfigurable real time embedded systems- design flow addresses the development of an holistic tool-chain for reconfigurable heterogeneous platforms. The entire tool-chain consists of three phases: algorithm exploration and translation, design space exploration and system synthesis. This paper evaluates the tools in the design space exploration phase and the system...
Building highly optimized embedded systems demands hardware/software (HW/SW) co-design. A key challenge in co-design is the design of HW/SW interfaces, which is often a design bottleneck. We propose a novel approach to HW/SW interface design based on the concept of bridge component. Bridge components fill the HW/SW semantic gap by propagating events across the HW/SW boundary and raise the abstraction...
This paper reports the design of two courses, "embedded hardware'' and "embedded software" offered in 2008 spring semester at Hiroshima University. These courses use 16-bit processor TINYCPU, cross assembler TINYASM, and cross compiler TINYC. They are designed very simple and compact: The total number of lines of the source code is only 427. Thus, students can understandthe entire design...
Hardware fault tolerance is a requirement even for noncritical applications, since unexpected failures may damage the reputation of manufacturers and limit the acceptance of their products. However, current practices for the design and deployment of hardware redundancy techniques remain in practice specific (defined on a case-per-case basis) and mostly manual. This paper addresses the challenging...
Recent research in the system level design field has produced a number of techniques for structuring the understanding of systems. Many of these techniques produce design structures that are easily expressible in Ada language. Ada language has a structure which allows the design of systems to be expressed independently of its implementation and thus can be a good system design language to use with...
The Kiwi system is targeted at making reconfigurable computing technology accessible to software engineers that are willing to express their computations as parallel programs. Our kiwic compiler takes .NET assembly language with suitable custom attributes as input and produces Verilog output which is mapped to FPGAs. In this brief paper, we describe attributes used to mark up I/O nets, embed assertions,...
Model-based verification is extensively begin used for accelerating the development of embedded system. However, by this approach, a model and actual RTL are required to be implemented separately, which increases the time required to ensure the equivalence of virtual models and actual hardware. To reduce the costs incurred in separate implementations, we propose to directly generate RTL from verification...
Hardware compilation flows use a high-level language like C++ or Java and translate it directly to an HDL. In this paper we propose to split the problem in two; first use a regular compiler to do the front-end processing, then use the generated machine code to produce the HDL. The MIPS-to-Verilog (M2V) compiler translates blocks of MIPS machine code into a hardware design represented in Verilog. M2V...
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