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Problem of telemetry and telecontrol data transmission systems noise immunity at endpoints implementing in the Internet of Things technology is considered. A method of improving streaming data encryption in open communication channels was proposed. The dynamic change of crypto key using non-linear feedback in shift register data and quasi-periodic reconfigure of the encoder / decoder device in data...
The features of weight-based sum codes for error detection in channel are discussed in this article. These features are acceptable for modification remote railway controlling systems such as locomotive signalization. In this article proposed the investigation for different coding modification algorithms, made an analysis of noise-immune properties when the modified Bauer code was replaced to modulo...
We design a multilevel data encoder for digital communication systems. Time constraints are imposed for a lot of services provided on portable devices. Hardware solutions are preferred more than software algorithms when the processing time and the power consumption are critical. Powerful error-correction coders processing multi-bit symbols can be implemented as hardware solutions in order to reduce...
The chance to influence the lives of a million children does not come often. Through a partnership between the BBC and several technology companies, a small instructional computing device called the BBC micro:bit will be given to a million children in the UK in 2016. Moreover, using the micro:bit will be part of the CS curriculum. We describe how Microsoft's Touch Develop programming platform works...
This paper investigates the performance of the BCH encoder and decoder for different error-correcting capabilities. The focus is on BCH codes of length 255. The motivation for this research is a project where data symbols of this length are transmitted over an error-prone wireless channel. The paper presents a mathematical introduction into encoding for cyclic codes and decoding of the BCH code. The...
In the HEVC standard, motion estimation is one of the most complex task of the video encoder, requiring a great percentage of the encoding time mainly due to (a) a large set of Coding Tree Unit partitioning modes, (b) the presence of multiple reference frames, and (c) the varying size of Coding Units in comparison with its predecessor H264/AVC. In addition, HEVC adopts Variable Block Size Motion Estimation...
In this paper, we present hardware and software implementations of flexible polar systematic encoders and decoders. The proposed implementations operate on polar codes of any length less than a maximum and of any rate. We describe the low-complexity, highly parallel, and flexible systematic-encoding algorithm that we use and prove its correctness. Our hardware implementation results show that the...
We present a new class of covert channels which can be created by utilizing common hardware but that cannot be detected by such. Our idea is to abuse anti-EMI features of a processor to create a covert channel on the physical layer. Thus, the sender uses the invariants in how digital signals are encoded over analog channels to covertly transport information. This leaked data is present on the wire...
High-level synthesis (HLS) promises high-quality hardware with minimal development effort. In this paper, we evaluate the current state-of-the-art in HLS and design techniques based on software references and architecture references. We present a software reference study developing a JPEG encoder from pre-existing software, and an architecture reference study developing an AES block encryption module...
A cyclic redundancy check (CRC) is an error-detecting code commonly used in data communication and storage devices to detect accidental changes to raw data. This paper provides an overview and principle of CRC. Emphasis is placed on the implementation of the CRC algorithm by method of hardware as well as software. It is proved that the implementation method present has high practical value.
Safety of embedded systems has the highest priority because it helps contribute to customer confidence and thereby ensures growth of the new markets, like electromobility. In series production fail-safe systems as well as fault-tolerant systems are realized with redundant hardware concepts like dual core microcontrollers running in lock-step-mode to reach highest safety requirements given by standards,...
Error correcting code (ECC) is an essential method in protection of NAND Flash memories. Complexity of it is increasing rapidly with the increment of error correction capability. Traditionally, the software implementation of ECC which has less cost and high flexibility is nearly ignored due to its inefficiency. This situation can be changed by design of faster software-based ECC scheme. We have found...
The matrix keyboard is taken as the basic input device of MCU or embedded systems. For traditional matrix keyboard, the number of interface signal lines connected to the MCU will rapidly increase with the rise of the number of keys. And it uses row scanning to get key values in software. But this situation is not suitable for MCU (Micro-programmed Control Unit) or embedded chips which have limited...
CVC4 is a solver for Satisfiability Modulo Theories (SMT). This tutorial aims to give participants an overview of SMT, describe the main features of CVC4, and walk through in-depth examples using CVC4 to demonstrate how to solve real problems with an SMT solver. We will provide a detailed description of various aspects of CVC4's internals, including its architecture, its capacity for dealing with...
The design and evolution of today's embedded systems face an increasing complexity both in the applications and in the platforms that support them. The use of complex platforms means that the engineers need to make non-trivial decisions during the design phase including optimized allocation, binding and scheduling. This situation creates a need for better ways to manage project complexity, and Model...
We present a fast implementation of the Deflate protocol that is substantially faster than the fastest version of the Zlib software package, yet maintains full compatibility to the Deflate standard. Our solution outperforms the fastest Zlib version by a factor of 2.6 and higher (in compression time) yet demonstrates only a negligible drop-off in terms of compression ratio. The basic building blocks...
IEEE-754 specifies interchange and arithmetic formats and methods for binary and decimal floating-point arithmetic in computer programming world. The implementation of a floating-point systemusing this standard can be done fully in software, or in hardware, or in any combination of software and hardware. This project propose VHDL implementation of IEEE-754 Floating point unit. In proposed work the...
Programming in embedded systems has always been a challenge. Highly-constrained nature of embedded devices invalidates conventional coding practices. The whole practice turns into a skill game that heavily depends on the personal skills and experience of the programmer. Embedded security applications are no exceptions. Efficient software implementation of symmetric cryptography primitives such as...
Dynamic Partial Reconfiguration allows to dynamically change the behaviour of a portion of the FPGAs by downloading new information in the configuration memory of the device. Since modern Systems-on-Programmable-Chips (SoPCs) make extensive use of this feature, many reconfigurable area are placed in the device, with several configurations for each area. This comes at a cost in terms of dependability...
The design of specialized hardware for Network Intrusion Detection has been subject of intense research over the last decade due to its considerably higher performance compared to software implementations. In this context, one of the limiting factors is the finite amount of memory resources versus the increasing number of threat patterns to be analyzed. This paper proposes an architecture based on...
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