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In order to apply the CPU to the control system for the renewable energy plant which is usually installed in the isolated place, there are a lot of issues e.g. the cooling, the power conservation and the parts exchange with the device life cycle. The undetectable dangerous error of the control system is also a big issue for such the isolated plant with the long term operation, because it causes the...
Fixed-width multipliers are widely used in digital signal processing (DSP) applications such as finite impulse response filter (FIR), fast Fourier transform (FFT) and discrete cosine transform (DCT). Baugh-Wooley multiplier is a preferred choice for the realization of 2's complement multiplication operation used in these applications. This paper presents the hardware realization and performance evaluation...
With the over-provisioned routing resource on FPGA, the topology choice for NoC implementation on FPGA is more flexible than on ASIC. However, it is well understood that the global wire routing impacts the performance of NoC on FPGA because the topology is routed by using fixed routing fabric. An important question that arises is: will the benefit of diameter reduction by using a highly connective...
We present a modified Built-In Self-Test (BIST) approach for programmable clock buffers in Xilinx Virtex-4, Virtex-5, and Virtex-6 Field Programmable Gate Arrays (FPGAs). While seemingly trivial, these critical clock buffer modules present interesting testing challenges as will be described in this paper. A timing problem was found in the previously reported BIST approach for the clock buffers, where...
FPGAs have been mainly used for designing of synchronous controllers. However, it is difficult to design asynchronous controllers on them because the circuit may suffer from hazard problems. This paper presents a method that implements a class of asynchronous controllers on FPGAs which are based on Look-Up Table (LUT) architectures. Asynchronous controllers specification used in heterogeneous (synchronous...
FPGAs are powerful platforms for investigating impending challenges associated with process scaling, such as variation and degradation. Their versatility allows us to gather empirical data and evaluate novel solutions. We carried out accelerated-life tests on modern FPGA devices and obtained a useful characterisation of the ageing processes that afflict them. We also quantified the potential benefits...
Field programmable logic is increasingly used to provide the high performance and flexible acceleration needed for network processing functions at multiple gigabit/second rates. Almost all such functions feature the use of clocks and timers in control and/or data roles, and these are typically implemented in an ad hoc manner. This paper introduces a set of three configurable timing modules that are...
A fast algorithm for modular inversion over GF(2m) using Fermat's Little Theorem is presented. A parallel modular multiplication algorithm and a cascade modular square block to reduce the times of modular exponentiation are given. Synthesis and implementation are realized in a Xilinx device of XC5VLX110T. By timing simulation, the clock frequency can achieve 50MHz. It is required to carry out one...
With the increasing NRE cost of advanced process technologies, reconfigurable devices receive great attention in small and medium volume IC designs. However, lower logic utilization and slower timing performance limit the efficacy of FPGA and CPLD. In this paper, we propose an efficient hybrid LUT/SOP reconfigurable design style to exploit both the advantages of LUT-cell and SOP-cell for circuit design...
In this paper, we present a configurable electrophoretic display (EPD) controller which provides a new architecture design of compacted waveform lookup tables. Compared with traditional designs of waveform LUT, the proposed method drastically shrinks the required memory size of LUTs. To improve visual quality, the controller also supports partial image update and integrates a real-time halftoning...
Electrophoretic displays (EPDs) have become the main solution to electronic paper because of its invariably reflective and bistable properties. With different requirements of display resolution, speed, and contrast ratio, the electronic paper (E-paper) designers may adopt different types of electrophoretic material and active matrix backplane for building the system. The driving waveforms should be...
As FPGAs follow Moore's law and increase in capacity and complexity, they are becoming more complex to use and are consuming increasing amounts of power. An interesting alternative for reconfigurable computing that is lower power and may be easier to program are massively parallel processor arrays (MPPAs). In this paper we investigate the Ambric AM2045, a commercial MPPA. To understand the differences...
All public key cryptosystems, though being highly secure, have a common drawback: They require heavy computational effort. This is due to the reliance on modular multiplication of large operands (1024 bits or higher). The same problem arises in data encryption/decryption and digital signature schemes. Examples of such cryptosystems are RSA, DSA, and ECC. Now considering embedded platforms for applications...
In this paper a common approach to design and testing of FPGA-based safety critical systems is given. The main idea for safety assurance and assessment of FPGA-based critical I&C systems lays in consideration of FPGA-chip as hardware and FPGA-project as software.
Although pipelining or C-slowing an FPGA-based application can potentially dramatically improve the performance, this poses a question for conventional reconfigurable architectures and CAD tools: what is the best way to support these new extra registers? While there have been multiple research efforts to address this problem, they generally impose strict architectural requirements, offer limited retiming...
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