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This paper presents a new method to implement the butterfly unit of FFT processor, based on the coordinate transformation and CORDIC algorithm. The butterfly unit uses less resource and reaches higher speed, also can be configured by parameter and satisfied by the real time operations. Finally, it can work on the frequency of 50 MHz after the design is downloaded to a chip EP2C20F484C7.
A FPGA-under-test has to be configured before it is tested. However, traditional configuration for a FPGA-under-test is time consuming due to the fact that the configuration has to be conducted manually many times until each resource of FPGA is not left behind. Automatic configuration generation for a FPGA-under-test implemented by an in-house SOC co-verification technology based FPGA functional test...
Based on the analysis for the requirement of the Field-Programmable Gate Array (FPGA) when the time interpolation time-to-digital converter (TDC) is planed to be applied in it, this paper describes a double sampling architecture for time interpolation TDC in the FPGA. The architecture extends the cover range of the delay-chain for twice, and can be implanted in those low-cost limited logic density...
A Network Sort Engine (NSE) that rapidly identifies the highest priority from numerous priorities is indispensable to enable per-flow queuing that supports massive queues in high-speed communications lines. This is because the bottleneck in per-flow queuing is the process to select a single queue to emit a frame from queues that are ready to emit frames; this process leads to sorting issues in identifying...
This paper designs a CMOS image acquisition and verification system based on FPGA, which integrates the function of image acquisition and image verification. The key technologies of this system are analyzed and verified, including the development of drive programming of CMOS sensor and experimentation on image display. This system can realize image acquisition and verify image collected from image...
Usage of multiple supply voltages has raised new design challenges in IC design. We focus on the problem of power aware placement when dual supply voltages provide two high performance and low power working modes on each FPGA tile. To meet timing constrains, all logic elements within a tile need to work in the high performance mode when at least one element within that tile has tight timing requirements...
Clock skew scheduling (CSS) is an effective technique to optimize clock period of sequential designs. However, these techniques are not effective in the presence of certain design structural constraints that limit the CSS. In this paper, we present an analysis of several design structural constraints that affect the CSS and propose techniques to resolve these constraints. Furthermore, we propose a...
Fast verification of the prototype design on software radio platform has become one of the most important research topics in communication systems. Based on OFDM receiver which is implemented on FPGA, the paper focuses on many key issues in the implementation of the strategy in software wireless platform such as OFDM frame synchronization, frequency compensation, symbol timing, etc. The proposed corresponding...
Block memory or custom memory is one of the most important features in the Structured ASIC design. But block RAM is not suitable to form small memory array and also limited to the pre-defined location. On the other hand, the distributed memory is one of the most important features in FPGA to support small size memory application and available anywhere across the chip. But the distributed memory is...
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