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This article mainly describes a way of designing a parallel and highly pipelined Cyclic Redundancy Code (CRC) generator. The design can handle five different channels at an input rate of 2Gbps each. The generated CRCS are compatible with the 32-bit Ethernet standards. This circuit has been implemented with the chip EP2C35F672C6 of ALTERA using the properties of Galois Field. The synthesis results...
Batcher's odd-even merging network can be easily implemented on hardware. And its parallel working between the comparator is very beneficial to play the advantages of hardware such as high efficiency and high speed. These make it as the most widely used sort algorithm. In this paper, FPGA is used to implement Batcher's odd-even merging network, solving the problems of traditional design. And the scalability...
Along with the rapid application of large-scale integrated circuit and computer system is growing by geometric series, the boundary between hardware and software has blurred. EDA, a novel technology arisen in recent years has been challenged with the traditional hardware design, because the original method and mode cannot satisfy modern hardware system design. In this paper, we implement the complex...
This paper introduces the principle of AES algorithm and the detailed description and implementation on FPGA. This system aims at reduced hardware structure. Compared with the pipeline structure, it has less hardware resources and high cost-effective. And this system has high security and reliability. This AES system can be widely used in the terminal equipments.
This paper uses the similarity between SHA-224 and SHA-256 algorithms to design the SHA-224/256 IP core oriented Digital Signature. The IP core uses parallel structure and pipeline technology to simplify the hardware design and improve the speed by 26%. Finally this IP core is implemented on the Altera’s FPGA EP2C20F484C6 chip. And its simulation result can run rightly under the 100MHz frequency....
This article is based on the new standard, uses the FPGA device opening, adopts FPGA technique of EDA to build 64 bits decimal floating multiplier model. And in this article, we mainly use DPD codec and BCD new codec and Signed-Digit radix-5 to process coefficient. At last, we use Decimal 32:2 CSA algorithm to process partial product. This effectively increases the computing speed and accuracy. As...
This article mainly describes a way of designing an efficient pseudo-random number generator. Combining that the cellular automaton has many characteristics, such as simple rules of the component units, the local connectivity of units, the high degree of parallelism in information processing, and the complicated global characteristics, we use the rule 30 of one-dimensional cellular automaton to drive...
This paper presents a new method to implement the butterfly unit of FFT processor, based on the coordinate transformation and CORDIC algorithm. The butterfly unit uses less resource and reaches higher speed, also can be configured by parameter and satisfied by the real time operations. Finally, it can work on the frequency of 50 MHz after the design is downloaded to a chip EP2C20F484C7.
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