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The ubiquitous computing era is characterized by wide deployment of resource constraint devices. Secure communication between such devices encounters a big challenge due to their resource limitation. The lightweight cryptographic algorithms are developed to address this challenge. In this work, implementation of LBlock, a lightweight encryption algorithm is investigated in Altera DE1 FPGA board. The...
A low noise, high speed board designed for drift chamber signals processing has been developed. The Front End electronics is a multistage amplifier based on high performance commercial devices. In addition, a fast readout algorithm for Cluster Counting and Timing purposes has been implemented on a Xilinx-Virtex 4 core FPGA. The algorithm analyzes and stores data coming from a Helium based drift cell...
This work presents a high-level synthesis methodology that uses the abstract state machines (ASMs) formalism as an intermediate representation (IR). We perform scheduling and allocation on this IR, and generate synthesizable VHDL. We have the following advantages when using ASMs as an IR: 1) it allows the specification of both sequential and parallel computation, 2) it supports an extension of a clean...
This paper presents the design and analysis high performance matrix filling for DNA sequence alignment accelerator using ASIC design flow. The objective of this paper is to design and analysis matrix module of DNA sequence alignment accelerator using clock cycle to get high performance. The scope of this paper is to optimize the DNA sequences alignment on the matrix filling module by implementing...
Traditional bilinear scaling method requires pre-zoom operation while zooming-out an image. In that way, the image resizing system will demand two different scaling sets, one for zooming-out and another for zooming-in, and hence leads to higher cost of hardware implementation and system complication. This paper presents an improved scaling method called window-scaling algorithm. It is relatively low...
A fast algorithm for modular inversion over GF(2m) using Fermat's Little Theorem is presented. A parallel modular multiplication algorithm and a cascade modular square block to reduce the times of modular exponentiation are given. Synthesis and implementation are realized in a Xilinx device of XC5VLX110T. By timing simulation, the clock frequency can achieve 50MHz. It is required to carry out one...
This paper presents a new method to implement the butterfly unit of FFT processor, based on the coordinate transformation and CORDIC algorithm. The butterfly unit uses less resource and reaches higher speed, also can be configured by parameter and satisfied by the real time operations. Finally, it can work on the frequency of 50 MHz after the design is downloaded to a chip EP2C20F484C7.
Although Triple Modular Redundancy (TMR) has been widely used to mitigate single event upsets (SEUs) in SRAM-based FPGAs, SEU-caused bridging faults between the TMR modules do not guarantee correctness of TMR design under SEU. In this paper, we present a novel approximation algorithm for resource binding on scheduled datapaths at the presence of TMR, which aims at containment of each SEU within a...
In this paper a common approach to design and testing of FPGA-based safety critical systems is given. The main idea for safety assurance and assessment of FPGA-based critical I&C systems lays in consideration of FPGA-chip as hardware and FPGA-project as software.
We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The design utilizes dedicated block multipliers as the main functional unit and block-RAM as storage unit for the operands. The adopted design methodology allows adjusting the number of multipliers, the radix used in the multipliers,...
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