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This paper describes research efforts to mitigate weaknesses in a TMR+spares radiation tolerant SRAM-based FPGA computer system. An existing 9-tile Microblaze architecture is reviewed and the desired improvements of fault-mitigated routing, fault location determination and performance enhancement via runtime-configurable hardware accelerators are discussed. Hamming encoding is proposed as a method...
The mitigation of single-event upsets (SEUs) through modular or functional redundancy is a traditional approach for designing fault-tolerant systems; however, even in multiple redundant systems, SEUs can lead to a system failure if they occur simultaneously. Previous fault-tolerant approaches have proposed run-time reconfiguration to regain the lost functionality. We worked with a similar strategy...
In this work, we have developed a fault-tolerant architecture which is compatible with existing island-style routing network. Due to this compatibility, the proposed architecture can not only be implemented easily in the existing FPGA devices but a new fault-tolerant FPGA device can also be fabricated without refining the existing routing architecture. A generic fault-tolerant Computation Cell is...
Generally, a programmable LSI such as an FPGA is difficult to test compared to an ASIC. There are two major reasons for this. One is that automatic test pattern generator (ATPG) cannot be used because of the programmability of the FPGA. The other reason is that the FPGA architecture is very complex. In this paper, we propose a new FPGA architecture that will simplify the testing of the device. The...
The very hight levels of integration and submicron device sizes used in current and emerging VLSI technologies for SRAM-based FPGAs lead to higher occurrences of defects and operational faults. Thus, there is a critical need for fault tolerance and reconfiguration techniques for SRAM-based FPGAs to increase chip reliability with field reconfiguration. We first propose a technique utilizing the principle...
Systems on Programmable Chips (SoPCs) are receiving an increasing interest from various application domains. Safety critical missions, driven by space and avionics applications, are especially attracted in using SoPCs due to low non-recurring engineering costs, reconfigurability and the large number of logic resources they provide. The capability of partial reconfiguration has recently become a promising...
Fault tolerance is an important system metric to increase chip reliability. The conventional technique for improving system reliability is through component replication, which usually comes at significant cost: increased design time, testing, power consumption, volume and weight. In this contribution, we propose a technique based on partial dynamic reconfiguration (PDR) to tolerate faults in configurable...
A position sensitive radiation sensor was modeled, developed and fabricated then interfaced with a field programmable gate array (FPGA) to create a radiation hardened computing platform. The system exploits environmental information from the sensor in order to determine regions within the FPGA that may have been affected by radiation. The spatial radiation sensor provides the computer system with...
A fault coverage method for digital system-on-chip by means of traversal the logic block matrix to repair the FPGA components is proposed. A method enables to obtain the solution in the form of quasioptimal coverage for all faulty blocks by minimum number of spare tiles. A choice one of two traversal strategies for rows or columns of a logic block matrix on the basis of the structurization criteria,...
The higher resiliency of Flash-based FPGAs to Single Event Upsets (SEUs) with respect to other non radiation-hardened devices, such as SRAM-based FPGAs, are increasing more and more their demand for avionic and space applications, where a harsh environment rich in ionizing radiation has to be faced. In this type of devices other transient faults tend to dominate over SEUs, especially when the device...
This paper presents the design of a many-core computer architecture with fault detection and recovery using partial reconfiguration of an FPGA. The FPGA fabric is partitioned into tiles which contain homogenous soft processors. At any given time, three processors are configured in triple modulo redundancy to detect faults. Spare processors are brought online to replace faulted tiles in real time....
Domain-partition (DP) model is a general model for reliability maximization problem under given redundancy. In this paper, an improved DP model is used to formulate a reconfiguration computing based fault tolerant system which is self-repairable in case of failure, and is solved as a nonlinear planning problem. The assumptions made in previous work are relaxed. An improved algorithm is proposed to...
The problem of planning the overlaps of multiple alternative configurations is critical to maximize the reliability of a reconfigurable fault-tolerant system based on field programmable gate arrays. To address the problem, an unnecessary assumption made in previous work is removed and a second-order approximation domain-partition method is proposed. Experimental results on ITC99 benchmark circuits...
Flash-based FPGAs are increasingly demanded in safety critical fields, in particular space and avionic ones, due to their non-volatile configuration memory. Although they are almost immune to permanent loss of the configuration data, they are composed of floating gate based switches that can suffer transient effects if hit by high energetic particles with critical consequences on the implemented logic...
Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous...
Field programmable gate arrays (FPGAs) are getting more and more attractive for military and aerospace applications, among others devices. The usage of non volatile FPGAs, like Flash-based ones, reduces permanent radiation effects but transient faults are still a concern. In this paper we propose a new methodology for effectively measuring the width of radiation-induced transient faults thus allowing...
In this paper, we present a novel technique for online testing of feedback bridging faults in the interconnects of the cluster based FPGA. The detection circuit will be implemented using BISTER configuration. We have configured the Block Under Test (BUT) with a pseudo-delay independent asynchronous element. Since we have exploited the concept of asynchronous element known as Muller-C element in order...
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