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RF-CMOS process employing 14nm FinFET technology is introduced for the first time and its RF performance is characterized. Compared with its 28nm planar counterpart, the optimized 14nm RF FinFET consumes 63% of DC power with 53% of device active area and 3.8 times higher intrinsic gain (gm/gds). Based on the 14 nm technology, VNCAP with higher cap density (8%) and Q-factor (23%) is also verified for...
Nowadays the spectrum regulations landscape is changing towards more flexible spectrum management schemes, such trends are expected to make additional spectrum resources available and lowers the spectrum access hurdles. In this paper, different spectrum aggregation scenarios have been compared focusing on the tradeoff between the total cost of ownership and the targeted QoS under different market...
This paper compares the amount of net energy used in the transmission segment of a multi-hop wireless relay network versus the single-hop system. It focuses on the computation of the power budget and is valid for half-duplex, full-duplex, downlink and uplink scenarios. The study shows that, contrary to a usual assumption today, the net amount of energy used by the multi-hop system may be higher than...
A 65 nm CMOS multistandard multiband mobile broadcasting receiver SoC that covers DAB/T-DMB, ISDB-T 1seg and FM is introduced. The SoC consists of RF/AFE, power management and demodulator. The power consumption is 35 mW with a die size of 2.9??2.9 mm2. The RF/AFE area is 2.3 mm2. The sensitivities are -103 dBm, -98 dBm, and 1 dBuV for T-DMB, 1 seg and FM, respectively.
Efficiency enhancement techniques in switched Class E power amplifier is usually obtained at the expense of the supply voltage. In cascode topology the supply voltage is limited by the breakdown voltage of the common-gate transistor. So a self biased technique is used at the common-gate to allow RF swing at the gate to boost the biasing voltage above VDD. This enables us to design the PA such that...
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