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This paper proposes readout circuits capable of sensing capacitance variations at the output of a capacitive sensor in the range of 0.5pF to 1.5pF using the concept of switched capacitance. Capacitive circuits are the most preferred for low power VLSI applications. We make use of a supply voltage of 1V as we intend to develop a low power module. This module will use the concept of programmable biasing...
This paper describes a 9-bit Successive Approximation Register Analog to Digital Converter (SAR-ADC) design in CMOS technology, particularly I4T, 0.35 μm, 45 V, used in automotive industry for sensor application. There are the individual analogue components of the SAR-DAC descibed in this paper: the Comparator, the R-2R Digital to Analog Converter (DAC) and the Operational Amplifier (OPA). The functionality...
Background: Domino logic is widely used in modern digital systems because of easy implementation with less number of transistors and high speed. The pre-charge and evaluation phases of the domino logic, leads to enormous transitions at the output. This switching of the output is undesirable as it leads to more dynamic power dissipation. Methods: This achieved by the using the structures such as True...
An Operational Transconductance Amplifier (OTA) with a novel dynamic-output control technique is proposed to achieve high slew rate (SR) performance in this work. The dynamic-output control technique utilizes two subtracters controlling the current sources to sink or source the output load adaptively. Moreover, as additional current sources are disabled in the DC operation status, the proposed structure...
The continuous growing demand of portable battery-powered electronics devices hunts for Nano-electronic circuit design for ultra-low power applications by reducing dynamic power, static power and short circuit power. In sequential circuit elements of an IC, a notable amount of power dissipation occurs due to the rapid switching of high frequency clock signals, which do not fetch any data bit or information...
This paper analyses the frequency limitations of an active rectifier for RFID applications that has been optimised for 13.56 MHz. The rectifier utilises an active MOS diode with threshold cancellation and a control scheme to reduce reverse leakage. The rectifier is implemented in AMS 0.35 µm CMOS and simulated in Cadence Spectre. For an input voltage of 2 V and an output current of 20 µA, a power...
In this paper, the design of sample and hold (S/H) circuit for 16 bit 100MS/s pipelined ADC is presented. A high performance and low power dissipation operational trans-conductance amplifier (OTA) is realized by optimizing circuit configuration and adopting switched-capacitor dynamic bias technology. A double gate-bootstrapping switch is used as the sample and hold switch to enhance the sampling linearity...
High power dissipation can occur by high launch-induced switching activity when the response to a test pattern is captured by flip-flops (FFs) in at-speed scan testing, resulting in excessive IR drop. IR drop may cause significant capture-induced yield loss in the deep-submicron era. It is known that test modification methods using X-identification and X-filling are effective to reduce power dissipation...
Data with increasing bandwidth requires future general-purpose as well as application specific microprocessors to improve performance endlessly. Transistor scaling, novel transistor structures, novel state-of-art VLSI design techniques and new computer architectures are the key drivers for boosting power and performance of microprocessors. Unfortunately, the processor cooling technique is unable to...
STT MRAMs are non-volatile memories potentially demonstrating high speed and integration density. These exclusive features of STT MRAMs are rapidly gaining attention of memory designers. They are strong contenders for futuristic embedded memory applications. Researchers have been primarily focusing on further decreasing the switching energy and increasing the integration density, while retaining the...
We propose an asynchronous-logic (async) Quasi-Delay-Insensitive (QDI) Static Logic Transistor-level Implementation (SLTI) approach for low power sub-threshold operation. The approach is implemented to design 32-bit pipelined Arithmetic and Logic Units (ALUs), the primary computation core for microprocessors, and benchmarked against the reported Pre-Charged Half-Buffer (PCHB). There are two key attributes...
Dual edge triggering is an effective method for reducing the power consumption in the clock distribution network. This paper compares two existing design of flip-flop CDMFF and CPSFF with the proposed design of the dual edge triggered flip-flop (DE-CPSFF). The design eliminates the redundant transitions of internal nodes when current data is same as the previous one using conditional technique. This...
Low leakage power switch is proposed to allow saving in power dissipation of the Network on Chip (NoC). The proposed NoC switch employs power supply gating to reduce the power dissipation. Two power reduction techniques are exploited to design the proposed switch. Adaptive Virtual Channel (AVC) technique is proposed as an efficient technique to reduce the active area using hierarchical multiplexing...
A low delay and speed efficient current mode Analog to Digital Converter has been described. The Analog to digital converter architecture generates 4-bit digital output in two stages. Different current comparator architectures have been used in the design and for each, the effect on the speed and area of the Analog to digital converter has been determined. Further, a power optimization technique has...
We describe modular voltage and current isolation schemes in a Power Management Integrated Circuit (PMIC) silicon platform. The isolation reduces the power dissipation during switching at the high side driver. It also suppresses the cross talk between power devices switching up to 60V at several Amps, and sensitive analog / digital circuitry on the same chip. Standard, buried layer and Isolated Drain...
As process technology continues to shrink, interconnect current densities continue to increase, making it ever more difficult to meet chip reliability targets. For microprocessors in the latest 32nm processes, interconnect wear-out via electromigration is as critical a design parameter, if not more so, as timing, power, and area, and must be planned for from the outset. This paper presents a true...
The Class-EF power amplifier (PA) introduced recently has a peak switch voltage much lower than the well-known Class-E PA. However, the value of the transistor output capacitance at high frequencies is typically larger than the required Class-EF optimum shunt capacitance. As a result, softswitching operation that minimizes power dissipation during OFF-to-ON transient cannot be achieved at high frequencies...
A low power switch design is proposed to achieve power-efficient Network on Chip (NoC). The proposed NoC switch reduces the power consumption of the Butterfly Fat Tree (BFT) architecture by 28 % as compared to the conventional BFT switch. Moreover, the power reduction technique is applied to different NoC architectures. The technique reduces the power consumption of the network by up to 41%. When...
Efficient power amplifiers are essentially needed in portable battery-operated systems such as mobile phones because the power amplifier is the most power consuming building blocks in the transmitter of these portable systems. This paper presents efficient techniques to increase the efficiency of the power amplifier as much as possible by degrading the power dissipation of the transistor in the mobile...
In this paper, we suggest a new behaviour for a MOSFET bidirectional switch for AC main application. We use two transistors of high voltage power MOSFET new technology based on the CoolMOS, one to control the forward current, and the second one to short-circuit the complementary diode, thus, for the first time, significantly decrease its power dissipation. For that, we must improve the power transistor's...
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