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This paper proposes readout circuits capable of sensing capacitance variations at the output of a capacitive sensor in the range of 0.5pF to 1.5pF using the concept of switched capacitance. Capacitive circuits are the most preferred for low power VLSI applications. We make use of a supply voltage of 1V as we intend to develop a low power module. This module will use the concept of programmable biasing...
With emerging high performance digital circuits, the need for data converters with high accuracy, high speed and low power for various kinds of applications has increased greatly. Extensive researches are being conducted in order to decrease the size of data converters to obtain low power and high speed characteristics. Digital to Analog Converters (DACs) convert digital signals to analog signals...
The design and analysis of a low power comparator that features an offset cancellation technique has been carried out in this paper. The proposed low power circuit works on a 1 GHz sampling frequency and is developed in 65nm CMOS technology. An offset cancellation technique and a switch are added to the comparator to reduce the offset and kickback noise. The comparator is implemented in a 5-bit Flash...
In this paper, a 16-channel analog front-end (AFE) ECoG-signal acquisition circuit for closed-loop seizure control system is presented. It is composed of 16 auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIA) with band-pass filters, 16 programmable transconductance-gain amplifiers, a multiplexer, a transimpedance amplifier, and a 10-bit SAR ADC. The low input-referred...
Background: Domino logic is widely used in modern digital systems because of easy implementation with less number of transistors and high speed. The pre-charge and evaluation phases of the domino logic, leads to enormous transitions at the output. This switching of the output is undesirable as it leads to more dynamic power dissipation. Methods: This achieved by the using the structures such as True...
Spin-transfer torque random access memory (STT-RAM) has emerged as an attractive candidate for future non-volatile memories. However, the write operation in 1T-1MTJ STT-RAM bit-cells is asymmetric and stochastic which leads to high energy consumption and long latency. In this paper, a new write assist technique is proposed to terminate the write operation immediately after switching takes place in...
A low voltage high-linearity ultra-wideband CMOS down-conversion mixer is designed. The third-order transconductance (gm3) cancellation techniques are utilized for improvement of the linearity of the mixer. In addition, the active loads and a switched buffer stage are used to increase the conversion gain. The designed mixer simulated by TSMC 0.18-μm CMOS technology achieves DC power consumption of...
The high demand of embedding more and more functionality in a single chip has enforced the use of scaling. As scaling drastically reduce the channel length the leakage current also increases significantly which increases the static power dissipation. A novel 8T-SRAM cell (Leakage Current Reduced SRAM cell) is proposed which reduces the leakage power dissipation significantly in comparison to the conventional...
This paper presents a low power D-latch designed using two low power tri-state MCML buffers. The proposed D-latch consumes less power as it makes use of low power tri-state buffers which promotes power saving due to reduction in the overall current flow in the circuit during the high impedance state. The proposed low power D-latch is simulated in PSPICE using 0.18μm TSMC CMOS technology parameters...
A low-energy 8-bit charge-redistribution SAR ADC for wireless sensor nodes is proposed. The ADC employs a new capacitor switching procedure that allows a reduction of the average switching energy as compared to previous proposals. Simulation and measurement results of a test chip prototype operating at 100 kS/s are provided, showing a SFDR of 55.63 dB for a power consumption of 2.17 μW. The active...
This paper presents a novel CMOS 6-transistor SRAM cell for different purposes including low power embedded SRAM applications and stand-alone SRAM applications. The data is retained by the cell with the help of leakage current and positive feedback, and does not use any refresh cycle. The size of the new cell is comparable to the conventional six-transistor cell of same technology and design rules...
Conventional magnetic logic using single-domain nanomagnets face severe challenges from power consumption, during field induced writing and clocking, and from poor selectivity over the logic cells. In this paper we report a novel CMOS integrated nanomagnetic logic architecture using Magnetic Tunnel Junctions (MTJs) as elemental cells. The integration details with 22nm CMOS technology is discussed...
This paper presents a case for using Nano-Electro-Mechanical-System switches for power gating idle functional units of an embedded microprocessor. We achieve an average of 26% total energy savings, with a worst-case 5% increase in cycles. Our work includes detailed comparison with transistor switches, actuation circuitry design, identification of desired switch parameters, and device lifetime analysis
A new low offset and high speed latch comparator is presented. The proposed offset compensation technique enables the preamplifier design relaxation for high-speed and high-resolution analog-to-digital converters. In order to enhance the loop gain of offset cancellation feedback the latch negative resistance is used. The Monte-Carlo simulation results for the designed comparator in 0.18μm CMOS process...
Low power design can be exploited at various levels, e.g., system level, architecture level, circuit level, and device level. This paper gives a brief overview of low power design principals, then focuses discussion on circuit level methods specifically state-of-the-art low power design techniques of clocking systems. Finally we discuss low power optimization techniques at system and architecture...
A study of the feasibility of a wide band double balanced resistive mixer in the 60 GHz band is done. The device is implemented in a 65nm CMOS technology process. In this paper an approach to design an optimized version of the mixer in terms of the principal figures of merit: conversion loss, port to port isolation and noise figure is shown. The mixer will be a part of an homodyne down-conversion...
The folding and interpolating ADC has speed advantage similar to flash ADC with reduced complexity. The folding amplifier can be used to produce more than one zero-crossing point to reduce required number of comparators. This paper presents simple low voltage, low power folding amplifier with folding factor=4 for folding and interpolating ADC. The design is implemented using 0.13 um technology at...
Power consumption is the bottleneck of system performance and is listed as one of the top three challenges in ITRS 2008. Low power design can be exploited at various levels, e.g., system level, architecture level, circuit level, and device level. This paper first gives a brief overview for low power optimization techniques at system and architecture level, then focus discussion on circuit level methods...
By analyzing the multi-valued switch-signal theory (MVSST), this paper presents a novel design scheme of low power ternary magnitude comparator (TMC). The scheme adopt switch-level design technique, on one hand, full-swing output signal improves noise margins, on the other hand, the reducing number of MOS insuring the simple circuit and small area. At last, the PSPICE simulation results indicate that...
Designing a power-gating structure with high performance in the active mode and low leakage and short wakeup time during standby mode is an important and challenging task. This paper presents a tri-modal switch cell that enables implementation of multimodal power gating, including active, data-retentive drowsy, and deep sleep modes. A circuit realization and design methodology are presented that allow...
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