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A modern smart battery charger is made of a Dc-Dc converter working in two modes: Charge and Boost. The Zero Cross Detector (ZCD) circuit is a highly important block in a Dc-Dc converter for achieving low switching losses. This paper presents a new approach to a ZCD converter which works by predicting the current through the inductor in DCM mode, based on the voltage across the diode during the conduction...
The design and analysis of a low power comparator that features an offset cancellation technique has been carried out in this paper. The proposed low power circuit works on a 1 GHz sampling frequency and is developed in 65nm CMOS technology. An offset cancellation technique and a switch are added to the comparator to reduce the offset and kickback noise. The comparator is implemented in a 5-bit Flash...
Analog-to-Digital converters plays vital role in medical and signal processing applications. Normally low power ADC's were required for long term and battery operated applications. SAR ADC is best suited for low power, medium resolution and moderate speed applications. This paper presents a 10-bit low power SAR ADC which is simulated in 180nm CMOS technology. Based on literature survey, low power...
Pulse generator serves an important role in gated ring oscillator (GRO) based Time-to-Digital converters (TDC) to enable the ring oscillator for the input time difference between two reference timing events. As the resolution of TDC advances to a few picoseconds, the linearity of the pulse generator becomes increasingly important. This paper reviews and compare between pulse generators implemented...
This paper proposes a compact spin transfer torque non-volatile flip-flop (STT-NVFF) design. The proposed NVFF adds four transistors and two complementary magnetic tunnel junctions (MTJs) over a standard volatile flip-flop with only 18% area overhead. The NVFF utilizes a low power/ fast switching MTJ that permits the elimination of the write circuitry existing in conventional STT-NVFFs. The proposed...
The continuous growing demand of portable battery-powered electronics devices hunts for Nano-electronic circuit design for ultra-low power applications by reducing dynamic power, static power and short circuit power. In sequential circuit elements of an IC, a notable amount of power dissipation occurs due to the rapid switching of high frequency clock signals, which do not fetch any data bit or information...
A 4-channel 4-bit flash analog-to-digital converter is presented with 10Gbps sampling speed and a figure-of-merit of 182 fJ/conversion-step. It uses a conventional clocking scheme, along with a modified sample-and-hold and comparator chain circuits that reduce the overall ADC power consumption, and enhances both the resolution and accuracy without the need for any digital calibration. The ADC is designed...
This paper describes an integrating analog to digital converter (iADC) based on the dual slope principle. This circuit was designed, fabricated and evaluated in course of a student project in the master degree program ISCD - Integrated Systems and Circuits Design of Carinthia University of Applied Sciences. The mixed-signal circuit consists of the analog front end with integrator and comparator stages,...
The design of a bi-state output buffer that can handle 5 times the supply voltage is presented. The use of self-biasing stacked devices driven by a cascade of complementary latches allows all devices to operate within the limits set by the technology, thus minimising any hot carrier injection and dielectric stress degradation. The presented voltage extension technique is scalable to larger and smaller...
A low latency and a low power comparator is presented in this paper. The concept of current aiding at the output nodes of SR latch is proposed to enhance the switching speed of the comparator. The current flowing through the output nodes of regenerative latch is sensed and the amplified difference of these two currents is applied to the output nodes of SR latch. The circuit is designed and simulated...
The effects of comparator input common-mode voltage Vcm are analyzed in this paper. The analysis clearly shows a trade-off in the choice of Vcm in terms of offset, noise, power and speed. Based on the analysis, an energy efficient SAR ADC switching technique is proposed with less Vcm variation and better linearity compared with the widely used monotonic switching technique. Both the simulation results...
This paper describes the design of a 6-bit 500 MS/s segmented current steering digital-to-analog converter (DAC) for telecommunication applications. The DAC is segmented as 4+2, where the 4 MSB bits are implemented in unary and 2 LSB bits are realized in binary architecture. The DAC is biased using an on-chip current reference to minimize the overall deviation in output due to temperature and supply...
This work presents the circuit level design of a non-volatile D-latch (NVDL) using memristor that retains the stored data in the event of power interruption. The programming complexity of proposed NVDL, unlike previous NV latches, is simplified. The proposed NVDL is designed using 32nm node and results are compared with the volatile CMOS based D-latch. Simulation results show that the proposed NVDL...
The effect of bias node voltage fluctuations on the performance of the current steering (CS) DAC is studied in this work. For that purpose a 10-bit segmented CS-DAC has been designed in 0.18 µm CMOS n-well technology provided by National Semiconductor. All current sources connected to the same bias cell act as correlated noise sources and generates more nonlinearity at the output. To improve the spurious...
Comparator is the main building block in ADC architecture. Main purpose of a comparator is to compare a signal with a reference signal and produce an output depending on whether the input signal is greater or smaller than reference. In this paper, a high speed high resolution comparator for use in sigma delta modulator is designed. The comparator is designed in a 0.35 um CMOS process with a supply...
A No Race (NORA) dynamic logic using neuron-MOS transistor is presented. The circuit is designed using the n-channel neuron-MOS transistor instead of the nMOS logic block or pMOS logic block in the conventional NORA dynamic logic circuit. The proposed full-adder shows that the logic block of NORA circuit can be simplified by utilizing neuron-MOS transistor. A simple synthesis technique of the n-channel...
This paper presents a low power D-latch designed using two low power tri-state MCML buffers. The proposed D-latch consumes less power as it makes use of low power tri-state buffers which promotes power saving due to reduction in the overall current flow in the circuit during the high impedance state. The proposed low power D-latch is simulated in PSPICE using 0.18μm TSMC CMOS technology parameters...
Serial communication facilitates the high-speed communication in gigascale systems. Serializer designs typically use the current-mode logic to achieve high speed at the cost of large power consumption. For the latches in the serializer, the power-hungry current-mode logic is replaced with differential cascaded pass-gate to reduce the power and delay. For the selectors in the serializer, the conventional...
This paper presents a 10-bit SAR ADC in 65 nm CMOS for medical implant applications. The ADC consumes 3-nW power and achieves 9.1 ENOB at 1 kS/s. The ultra-low-power consumption is achieved by using an ADC architecture with maximal simplicity, a small split-array capacitive DAC, a bottom-plate sampling approach reducing charge injection error and allowing full-range input sampling without extra voltage...
In this paper, we design a 1-kbit antifuse OTP (one time programmable) memory IP which is used for power management ICs. A conventional antifuse OTP cell using a single VPP (positive program voltage) has a problem about applying a higher voltage than the breakdown voltage to thin gate oxides and securing the reliability of MV (medium voltage) devices which are thick gate transistors at the same time...
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