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This paper investigates the effect of snubber capacitor on the zero voltage switching (ZVS) boundary of the dual active bridge (DAB) DC-DC converter. The analysis is performed to determine the minimum current required during transistor turn-off to achieve successful ZVS and the ZVS boundary operating conditions of the converter are obtained. The operation of the converter during transistor turn-off...
In this paper, a new design for efficiency enhance switching-capacitor DC-DC voltage converter based on combination of traditional charge-transfer-switch charge pump and cross-coupled output stage. In order to get a high output power and pump-efficiency. By using multi-phase technique, its can increase both of pump-efficiency and power-efficiency. The propose multi-phase mixed-structure charge pump...
In this paper, the transistor sizing of an auxiliary output stage in a digitally controlled transient suppression system for fully integrated point-of-load (POL) DC-DC converters is investigated. The auxiliary output stage is added in parallel to the main output switching stage to help reduce output voltage deviation during load transient. The sizing of the auxiliary output stage in relation to the...
This paper is focused on the high-voltage (ges2 kV) high-power (ges20 kW) isolated DC/DC converters for the rolling stock applications. The 3.3 kV IGBT based three-level half-bridge neutral point clamped (NPC) inverter topology was analyzed as an alternative to the two-level half-bridge with 6.5 kV IGBTs. The properties of primary switches, theirs selection procedure as well as inverter loss distribution...
An enhanced high-efficiency switching-capacitor DC-DC voltage converter based on the combination of charge transfer switch (CTS) charge pump and cross-coupled output stage is presented. Some motivated methods to overcome the reverse charge sharing problem of traditional CTS charge pump are discussed and a new mixed structure is proposed to conquer the remaining problem of threshold drop at the output...
A 900-nA quiescent current buck converter is implemented in standard 0.25 mum CMOS technology. The controller's analog subblocks are designed to operate in weak-inversion region to reduce quiescent current. It also implements internal compensation circuit to minimize external passive components. In order to reduce the size of an on-chip capacitor, the Miller effect is utilized. The measurement results...
This paper proposes a novel DC-DC converter: the DC-DC multilevel voltage multiplier (MVM). An Nx MVM can be built with two switches, 2N-2 diodes and 2N-2 capacitors, free of magnetic components. It is based on the multilevel converters principle and designed for unidirectional power transfer applications. Each device blocks one voltage level, then high voltage converters can be synthesized with low...
Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large capacitor is wasted. Instead, the energy can be recovered using an on-chip DC-DC converter. This paper investigates the integration of two DC-DC converter topologies, boost and buck-boost, with a high-speed clock driver. The...
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