The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A novel 'decoupled C-V' technique is proposed to characterize the channel and overlap capacitances of miniaturized MOSFET's. This method successfully decouples channel capacitance from overlap capacitance in submicron CMOS devices. The intrinsic channel capacitance can be well modeled by the quasi-static C-V theory. It allows the accurate determination of the effective channel length and effective...
The simple approach of thermal oxide capped poly refill trench isolation (Rung et al., 1982) is studied with regard to the impact of cap oxide thickness, trench wall thermal oxide thickness, and trench depth on MOSFET and isolation characteristics. It is shown that an increase of cap oxide thickness (t/sub ox/) from 600 to 2000 AA eliminates subthreshold double-hump phenomena, improves isolation V/sub...
Complementary 0.15 mu m MOSFETs and double-diffused lateral BJTs have been successfully integrated in a 10-mask CBiCMOS process, by utilizing the process simplifications that are unique to thin-film SOI. The CMOS devices are built in a SIMOX silicon layer of intermediate thickness (130 nm), leading to nearly-fully-depleted (NFD) characteristics. Excellent short-channel behavior is observed down to...
A BiCMOS technology is described that is built on an optimized 3.3-V 0.5-μm CMOS base process. A high-performance single-polysilicon npn transistor with a cutoff frequency of 15 GHz is integrated using CMOS-compatible heat cycles. Novel level-shifted BiCMOS circuit techniques are employed to allow the bipolar devices to operate at a higher voltage (4.1 V) without performance degradation while...
The authors report the design and evaluation of a self-contained CMOS integrated ISFET (ion-sensitive field effect transistor) pH sensor. They demonstrate two technological solutions for the implementation of a microelectronic ISFET pH sensor: (1) a standard-CMOS-compatible process for fabricating the ISFET and CMOS analog circuits on the same chip has been developed and (2) the electrical reference...
A novel, simple LOCOS (local oxidation of silicon) technology has been developed for 0.5- mu m MOS devices. Using the technology, channel-stop implantation and deep-channel implantation are performed simultaneously after field oxidation. These self-aligned implantations eliminate the lateral diffusion of the channel stop impurities, thus suppressing narrow-width effects. Moreover, the body effects...
The performance of a mesa-isolated CMOS technology fabricated on ultrathin (nonepitaxial) SOI (silicon on insulator) with film thickness ranging from 850 to 1800 AA is presented. Overall the data show that there is no observable reduction in surface mobility as the silicon thickness is reduced to 850 AA, indicating that the scaling of devices into the deep-submicron regime is possible. The results...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.