The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Mobile ion contamination in the deep-submicron regime was studied for boron, arsenic, and phosphorus-doped polysilicon gates. An effective gettering process is presented for the passivation of p+ polysilicon gates without boron penetration through thin gate oxide. The issue of mobile ion gettering with p+ polysilicon in deep-submicron CMOS technology is also studied. A channel-length-dependent mobile...
A single-transistor advanced contactless EEPROM (ACEE) array technology with an 8.6 μm2 cell developed for a single-power-supply 5-V only 4-Mb flash EEPROM is described. This ACEE technology has 0.8 μm minimum lithographic feature sizes and a novel sublithographic remote tunnel diode structure. Low-voltage isolation between bitlines of the same cell has been achieved by diode isolation...
An EPROM cell structure is described that uses folded word lines with double Al layers. Cell characteristics are optimized to obtain high-speed access. The data retention reliability and erasability are studied, focused on a 2Al metallization process. The feasibility of the technology has been confirmed by a 1-Mb CMOS EPROM device which shows 16 ns access time and extremely high data retention reliability...
The effect of the nitrogen atoms in the gate oxide and why gate oxide nitridation acts oppositely on the n- and p-MOSFET mobilities were studied. It was found that the mobility changes for the oxide/nitride/oxide (ONO) gate MOSFETs are not caused by the high-temperature process during the rapid thermal process (RTP), but rather are caused by the involvement of the nitrogen atoms in the gate oxide...
A programming technology is proposed to improve the endurance and read retention characteristics of NAND-structured EEPROM cells programmed by Fowler-Nordheim tunneling of electrons. Erasing and writing are accomplished uniformly over the whole channel area instead of nonuniform erasing at the drain. To achieve programming over the whole channel area, a new device structure is also proposed. The high-voltage...
Experimental results are presented for a WSi2/TiN compound-gate MOSFET with a near-midgap work function ranging from 4.63 to 4.75 eV and low resistivity. Sheet resistances of the compound gate and the conventional n+ gate with and without the interconnection layer are studied, and it is shown that the compound gate materials are an adequate interconnection layer. When positive bias is applied to the...
A positive resist with high sensitivity and stability named ASKA (Alkaline Soluble Kinematics using Acid generator) is described. A KrF excimer laser with a maximum laser power of 8.8 W and more than 109 pulses named PCR (polarization coupled resonator) is also presented. The result of KrF excimer laser lithography for 0.4-μm VLSI using this combination of ASKA and PCR technologies indicates...
Work on forming high-quality TiN barrier layers by low-pressure chemical vapor deposition (LPCVD) in deep-submicron contacts is reported. A high-quality titanium nitride film was prepared by the photo-assisted LPCVD method using a new organo-titanium compound, Cp2Ti(N3)2, that does not contain chlorine atoms. The film exhibits sufficient barrier effect to withstand 450°C annealing as well...
Experimental results for maximum cut-off frequency (fT) values of 75 and 52 GHz were achieved for SiGe-base and Si-base bipolar transistors with intrinsic base sheet resistances in the 10-17 kΩ/square range. These results extend the speed of silicon bipolar devices into a regime previously reserved to GaAs and other compound semiconductor technologies. Excellent junction characteristics...
A major limitation of the lightly-doped-drain (LDD) type of structure at deep submicron (⩽0.35 μm) dimensions is studied and a new structural approach for successfully achieving reliable and manufacturable MOSFETs for L⩽0.35 μm is described. The newly reported limit on maximum junction depth and allowable grading of the doping profile of the N-region results from the...
A technology is proposed for the fabrication of three-dimensional integrated circuits (3D-ICs) having a large number of device layers, referred to as `cumulatively bonded IC' (CUBIC) technology wherein several thin-film devices are bonded cumulatively. The technology was used to fabricate a two-active-layer device having a bulk-Si NMOSFET lower layer and a thinned NMOSFET upper layer. The CUBIC technology,...
A BiCMOS technology is described that is built on an optimized 3.3-V 0.5-μm CMOS base process. A high-performance single-polysilicon npn transistor with a cutoff frequency of 15 GHz is integrated using CMOS-compatible heat cycles. Novel level-shifted BiCMOS circuit techniques are employed to allow the bipolar devices to operate at a higher voltage (4.1 V) without performance degradation while...
A BiCMOS structure called SST-BiCMOS is proposed. In this structure, a high-performance emitter-base self-aligned bipolar technology using double polysilicon layers called SST and a submicron-gate-length lightly doped-drain MOS technology are used. This structure was used to realize high-performance BiCMOS technology with a cutoff frequency of 20 GHz, an NPN transistor, a propagation delay time of...
A unified delay model is presented that predicts BiCMOS gate delay for both long- and short-channel MOSFETs, in low-level and high-level injection in the bipolar junction transistors (BJTs), for 5 V and reduced supply and over a wide range of circuit parameter variation. The model is applied to devise circuit and device design strategies to optimize gate performance at 5 V and at scaled supply voltage...
An advanced BiCMOS technology (ABiC IV), developed by integration of high-performance CMOS devices with a state of the art bipolar process, is presented. The core bipolar process is the fourth generation of the advanced single poly emitter coupled technology (ASPECT). Gate delays of 47 psec, 110 psec and 120 psec have been achieved for unloaded ECL, CMOS and BiCMOS gates, respectively. In addition...
Hot carrier effects of a buried pMOSFET in the retrograde n-well have been investigated. A new phenomenon, a spill-over effect of avalanche-generated electrons into the bulk, was discovered. This effect is inherent in pMOSFETs fabricated in the n-well with high doping. It is shown that the effect reduces the hot-electron-induced device degradation even with high hot-electron generation
The deficiencies of BiCMOS logic are analyzed, and the addition of a high-performance vertical pnp to the BiCMOS technology, henceforth called complementary BiCMOS technology, is considered as a solution. It is suggested that density problems associated with BiCMOS logic can be alleviated by replacing the conventional BiCMOS logic circuit, i.e. the `totem-pole' circuit, with a simpler complementary...
A method of high-performance and simple fully complementary bipolar MOS (FCBiMOS) process integration is proposed that is compatible with a conventional 0.5-μm CMOS and BiCMOS process. This process is based on two key technologies. One is a high-dose boron MeV ion implantation combined with an epitaxial wafer. The other is rapid thermal processing (RTP) for high current gain. It has been confirmed...
Fabricating shallow p+-n junctions by low energy BF2 implantation, especially using furnace annealing, requires preamorphous implantation of crystalline silicon to eliminate the boron channeling and the suppression of diffusion in heat cycles. A preimplantation technique is presented that uses fluorine to influence the electric characteristics of p-channel MOSFETs. Using heat cycling of 850°C...
To realize high performance mixed analog and digital ASICs, a novel CBi-CMOS technology is proposed. This technology, called DIIP (double-implanted and isolated P-well) CBi-CMOS technology, is characterized by a structure with vertical NPN, PNP and CMOS structures on the same chip. In this structure, a vertical PNP transistor and NMOS transistor are fabricated in a P-well, which is isolated from the...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.