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A diffusion model for ion-implanted BF/sub 2//sup +/ ions in Si for rapid thermal annealing application has been developed based on the effects of defect evolution on dopant diffusion. In addition, a simple, accurate and universal precipitation model has been developed for high dose implantation. Simulation results show excellent agreement with the experimental results.<<ETX>>
An analog VLSI implementation which mimics the early visual processing stages in insects is described. The system is composed of sixty parallel channels of integrated photodetectors and processing elements. It serves as the front end processor for a motion detection chip. The photodetection circuitry includes p-well junction diodes on a 2 mu m CMOS process and a logarithmic compression to increase...
A 2- mu m CMOS IC interfaces directly to the output of a CCD, level shifts the signal, amplifies it by a 4-bit programmable gain of up to 20 dB, and corrects the offset per pixel with a 3-bit word. A non-reset video output is obtained with an internal time-interleaved architecture. The total harmonic distortion (THD) of -50 dB is obtained at 15 MHz clock rates and +or-3.3 V full scale outputs. The...
A new circuit implementation of the Kohonen neural networks is proposed. A novel winner-take-all circuit is developed and digital counters are used to store and update the weights. An experimental chip of this system has been fabricated by 1.2 mu m CMOS technology. A architecture is also proposed for these chips to be combined together to form a larger net.<<ETX>>
A new macromodel-based reliability diagnosis program (iRULE) is presented for design of hot-carrier resistant VLSI circuits. iRULE detects first the potentially critical transistors by using netlist- and geometry-based rules and then determines the criticality of hot-carrier degradation in those transistors by using macro-models. The algorithmic complexity of iRULE is shown to be linear with respect...
Effects of residual surface nitrogen, remaining after stripping off oxynitrides (N/sub 2/O-grown or NH/sub 3/-nitrided oxides), on the quality of the regrown gate oxides are studied. Residual surface nitrogen is observed to reduce the breakdown field and degrade the TDDB characteristics of the subsequently grown gate oxides. Results show that oxide regrowth in N/sub 2/O, rather than O/sub 2/, can...
Sub-quarter micrometer PMOSFET's are fabricated on SOI films, exhibiting excellent short channel behavior low source-drain resistance, and remarkably large current drive and transconductance. For T/sub ox/=5.5 nm, saturation transconductances of 270 mS/mm at 300 K and 350 mS/mm at 80 K are achieved, which are the highest reported values for this oxide thickness. Direct measurements and simulation...
The gate-and-drain fully-overlap LATID (Large-Tilt-Angle Implanted Drain) structure has been proposed recently and been used in submicron MOS device design to suppress the spacer-induced degradation and improve the device current drivability. So far, none has been provided to study quantitatively the hot carrier effect for various device process conditions such as the implantation of n/sup -/ dosage...
A novel high density full feature EEPROM cell with minimum process complexity is proposed. The new structure is a contactless cell with buried N+ bit lines. The floating gate is self aligned to the word line, using self aligned stacked etch technology. Strong reduction of contacts number and cell area is achieved with respect to the conventional Flotox cells. Electrical characteristics and reliability...
An accurate and efficient physical simulation method, based on a 2-D energy transport model and Monte Carlo calculated hot electron energy distribution, has been used to simulate the read-disturb lifetime reduction of deep-submicron EPROM devices. This method has been validated by data of a 0.5 mu m EPROM technology and used to predict the read disturb lifetime for the 0.35 mu m technology generation...
A 2-D grid generator, EGG (Erso Grid Generator), is proposed to reconstruct the bad-shaped grid generated by SUPREM-4. EGG uses the fuzzy scheme to generate the rectangle-based grid. With this scheme the grid is generated as well-shaped as possible and the grid number is as small as possible to resolve the geometry features. It is shown that the difficulty in grid generation has been overcome for...
DC lifetime, in conjunction with speed and time factors, can be used to predict digital circuit hot-carrier lifetime. Analog circuit reliability prediction, on the other hand, has to take analog design variables such as channel length, biasing conditions, and circuit topography into consideration. The authors propose a new methodology for predicting analog circuit reliability. Instead of the traditional...
The problems of prematured snapback and false multiple breakdown are found in simulating semiconductor devices in the high temperature region. The only way to achieve accurate and efficient electrothermal simulation under these conditions is by adaptive regridding. An adaptive regridding algorithm that approaches the optimal efficiency by applying the equidistribution of local truncation error is...
The dependence of performance and parasitic resistances on source/drain implant anneal conditions and on back-end-of-line maximum temperature is evaluated for (1) salicided CMOS using n/sup +//p/sup +/ poly gates with surface channel PMOS and for (2) unsalicided CMOS using all n/sup +/ poly gates with buried channel PMOS. The gate oxide thickness used is 6 nm. Both the NMOS and PMOS effective channel...
ESIM is developed based upon physical-oriented model for deep submicron LDD CMOS technology. The effects of bias-dependent series resistance and nonuniform channel profile and the geometry dependence of MOSFET are well specifically built into ESIM equation. The 1-st derivatives of ESIM I-V curves are always continuous for all bias regions. Therefore, ESIM can be applied to sub- mu m mixed-mode circuit...
Process/device synthesis using automated optimized device design with a set of target/constraint values is investigated to reduce device design time and product cycle time. As a first step, the authors report results on (a) transistor design methodology, (b) TCAD simulator tuning methodology, and (c) device optimization using process sensitivity considerations and a new transistor figure-of-merit...
A low voltage option in a 0.5 mu m CMOS process technology is described. The key technological issue is the threshold voltage and sub-threshold leakage characteristics of the PMOS devices. The device properties of the n/sup +/-gate buried channel devices are compared with the corresponding p/sup +/-gate surface channel devices. For power supply voltages down to 0.9 V the surface channel PMOS devices...
The ESD robustness of LATID (Large Angle Tilted Implanted Drain) MOSFET for I/O drivers is evaluated and found inadequate for deep submicron 5 V CMOS technology. Alternative drain structures are examined and reported to meet the ESD and other criteria. An additional phosphorous implant that creates a LATID/DDD (Double Diffused Drain) structure meets all ESD and device criteria.<<ETX>>
This paper describes a single chip solution of the JPEG standard's baseline system. A VLSI architecture is proposed to get better trade-off between chip size and performance. The IC is implemented in a 1.0 mu m CMOS process with a die size of 11.2*10.8 mm/sup 2/.<<ETX>>
The two-dimensional discrete Fourier transform, (2-D DFT) is commonly employed in image processing systems. In this paper, a new systolic architecture is proposed for fast computation of the 2-D DFT. The system is constructed by using a recursive algorithm to compute the separable 2-D discrete Hartley transform (DHT) and then converting the result into the 2-D DFT. It possesses the features of regularity...
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