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As CMOS scaling is approaching 0.1 mu m channel length, the authors examine a number of key device and technology issues which will ultimately determine the limit of room temperature scaling. High speed and high transconductance (750 mS/mm for n, 400 mS/mm for p) sub-0.1 mu m nMOSFET and pMOSFET devices have recently been demonstrated. P/sup +/ polysilicon gate was used on 35 AA gate oxide without...
A BiCMOS technology is described that is built on an optimized 3.3-V 0.5-μm CMOS base process. A high-performance single-polysilicon npn transistor with a cutoff frequency of 15 GHz is integrated using CMOS-compatible heat cycles. Novel level-shifted BiCMOS circuit techniques are employed to allow the bipolar devices to operate at a higher voltage (4.1 V) without performance degradation while...
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